The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.07 - July (2011 vol.60)
pp: 992-1005
Vladimir Uzelac , The University of Alabama in Huntsville, Huntsville
Milena Milenković , IBM, Austin
Aleksandar Milenković , The University of Alabama in Huntsville, Huntsville
ABSTRACT
The increasing complexity of modern embedded computer systems makes software development and system verification the most critical steps in system development. To expedite verification and program debugging, chip manufacturers increasingly consider hardware infrastructure for program debugging and tracing, including logic to capture and filter traces, buffers to store traces, and a trace port through which the trace is read by the debug tools. In this paper, we introduce a new approach to capture and compress program execution traces in hardware. The proposed trace compressor encompasses two cost-effective structures, a stream descriptor cache, and a last stream predictor. Information about the program flow is translated into a sequence of hit and miss events in these structures, thus dramatically reducing the number of bits that need to be sent out of the chip. We evaluate the efficiency of the proposed mechanism by measuring the trace port bandwidth on a set of benchmark programs. Our mechanism requires only 0.15 bits/instruction/CPU on average on the trace port, which is a sixfold improvement over state-of-the-art commercial solutions. The trace compressor requires an on-chip area that is equivalent to one third of a 1 kilobyte cache and it allows for continual and unobtrusive program tracing in real time.
INDEX TERMS
Compression technologies, real time and embedded systems, testing and debugging, tracing.
CITATION
Vladimir Uzelac, Milena Milenković, Aleksandar Milenković, "Caches and Predictors for Real-Time, Unobtrusive, and Cost-Effective Program Tracing in Embedded Systems", IEEE Transactions on Computers, vol.60, no. 7, pp. 992-1005, July 2011, doi:10.1109/TC.2010.146
REFERENCES
[1] B. Dipert, "Inside Apple's iPhone: More than Just a Dial Tone," EDN, http://www.edn.com/articleCA6457065.html?nid=2551 , Sept. 2009.
[2] J. Messina, "Multi-Core ARM Chips Slated for Smartphones Next Year," http://www.physorg.comnews164386074.html , Sept. 2009.
[3] C.J. Murray, "Automakers Aim to Simplify Electrical Architectures," http://www.designnews.com/article316784- Automakers_Aim_to_Simplify_Electrical_Architectures.php , Sept. 2009.
[4] M. Abramovici, P. Bradley, K. Dwarakanath, P. Levin, G. Memmi, and D. Miller, "A Reconfigurable Design-for-Debug Infrastructure for SoCs," Proc. 43rd Design Automation Conf., pp. 7-12, 2006.
[5] RTI Int'l, "The Economic Impacts of Inadequate Infrastructure for Software Testing," http://www.nist.gov/director/prog-ofc report02-3.pdf , July 2009.
[6] A.B.T. Hopkins and K.D. McDonald-Maier, "Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores," IEEE Trans. Computers, vol. 55, no. 2, pp. 174-184. Feb. 2006.
[7] ARM, "Embedded Trace Macrocell Architecture Specification," http://infocenter.arm.com/help/topic/com.arm.doc.ihi0014o IHI0014O_etm_v3_4_architecture_spec.pdf , Nov. 2009.
[8] MIPS, "The PDTrace™ Interface and Trace Control Block Specification," http://www.mips.com/products/product- materials/ processormips-architecture/, Nov. 2009.
[9] Infineon, "TC1775 System Units 32-Bit Single-Chip Microcontroller," http://www.infineon.com/cms/en/productchannel. html? channel=ff80808112ab681d0112ab6b7535083b , Nov. 2009.
[10] Freescale, "MPC555/MPC556 User's Manual," http://www.freescale.com/files/microcontrollers/ doc/user_guideMPC555UM. pdf, Nov. 2009.
[11] IEEE-ISTO, The Nexus 5001 Forum Standard for a Global Embedded Processor Debug Interface, http:/www.nexus5001.org, Nov. 2009.
[12] W. Orme, "Debug and Trace for Multicore SoCs," ARM White Paper, 2008.
[13] C.-F. Kao, S.-M. Huang, and I.-J. Huang, "A Hardware Approach to Real-Time Program Trace Compression for Embedded Processors," IEEE Trans. Circuits and Systems, vol. 54, no. 3, pp. 530-543, Mar. 2007.
[14] M. Milenković, A. Milenković, and M. Burtscher, "Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces," Proc. Data Compression Conf., pp. 55-65, 2007.
[15] M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, and R.B. Brown, "MiBench: A Free, Commercially Representative Embedded Benchmark Suite," Proc. IEEE Fourth Workshop Workload Characterization, 2001.
[16] A.R. Pleszkun, "Techniques for Compressing Program Address Traces," Proc. 27th Ann. Int'l Symp. Microarchitecture, pp. 32-39, 1994.
[17] A. Milenković and M. Milenković, "Exploiting Streams in Instruction and Data Address Trace Compression," Proc. IEEE Sixth Ann. Workshop Workload Characterization, pp. 99-107, 2003.
[18] A. Milenković and M. Milenković, "An Efficient Single-Pass Trace Compression Technique Utilizing Instruction Streams," ACM Trans. Modeling and Computer Simulation, vol. 17, pp. 1-27, 2007.
[19] T. Austin, E. Larson, and D. Ernst, "Simplescalar: An Infrastructure for Computer System Modeling," Computer, vol. 35, pp. 59-67, 2002.
[20] V. Uzelac, A. Milenković, M. Milenković, and M. Burtscher, "Real-Time, Unobtrusive, and Efficient Program Execution Tracing with Stream Caches and Last Stream Predictors," Proc. 27th IEEE Int'l Conf. Computer Design, pp. 173-178, 2009.
[21] Intel, "Intel Xscale Core Developer's Manual," 2004.
[22] N. Muralimanohar, R. Balasubramonian, and N.P. Jouppi, "Cacti 6.0: A Tool to Model Large Caches," HP Laboratories, 2009.
57 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool