Caches and Predictors for Real-Time, Unobtrusive, and Cost-Effective Program Tracing in Embedded Systems
Issue No.07 - July (2011 vol.60)
Aleksandar Milenković , The University of Alabama in Huntsville, Huntsville
Vladimir Uzelac , The University of Alabama in Huntsville, Huntsville
Milena Milenković , IBM, Austin
Martin Burtscher , The University of Texas at Austin, Austin
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.146
The increasing complexity of modern embedded computer systems makes software development and system verification the most critical steps in system development. To expedite verification and program debugging, chip manufacturers increasingly consider hardware infrastructure for program debugging and tracing, including logic to capture and filter traces, buffers to store traces, and a trace port through which the trace is read by the debug tools. In this paper, we introduce a new approach to capture and compress program execution traces in hardware. The proposed trace compressor encompasses two cost-effective structures, a stream descriptor cache, and a last stream predictor. Information about the program flow is translated into a sequence of hit and miss events in these structures, thus dramatically reducing the number of bits that need to be sent out of the chip. We evaluate the efficiency of the proposed mechanism by measuring the trace port bandwidth on a set of benchmark programs. Our mechanism requires only 0.15 bits/instruction/CPU on average on the trace port, which is a sixfold improvement over state-of-the-art commercial solutions. The trace compressor requires an on-chip area that is equivalent to one third of a 1 kilobyte cache and it allows for continual and unobtrusive program tracing in real time.
Compression technologies, real time and embedded systems, testing and debugging, tracing.
Aleksandar Milenković, Vladimir Uzelac, Milena Milenković, Martin Burtscher, "Caches and Predictors for Real-Time, Unobtrusive, and Cost-Effective Program Tracing in Embedded Systems", IEEE Transactions on Computers, vol.60, no. 7, pp. 992-1005, July 2011, doi:10.1109/TC.2010.146