This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
On Using Lossy Compression for Repeatable Experiments during Silicon Debug
July 2011 (vol. 60 no. 7)
pp. 937-950
Ehab Anis Daoud, McMaster University, Hamilton
Nicola Nicolici, McMaster University, Hamilton
The amount of data that is observed during at-speed silicon debug is limited by the capacity of the on-chip trace buffers. To increase the debug observation window, we propose a low-cost debug architecture for at-speed silicon debug based on lossy compression. The proposed architecture enables a new debug methodology that accelerates the identification of the erroneous samples that occur intermittently over a long observation window by avoiding debug experiments that capture only error-free data. The proposed solution is applicable to both automatic test equipment-based debug and in-field debug on application boards, as long as the debug experiments are repeatable and the reference data at the probe signals are deterministically computed using a fast behavioral model of the circuit under debug.

[1] E. Anis and N. Nicolici, "Low Cost Debug Architecture Using Lossy Compression for Silicon Debug," Proc. Conf. Design, Automation, and Test in Europe (DATE), pp. 225-230, Apr. 2007.
[2] W.K. Lam, Hardware Design Verification: Simulation and Formal Method-Based Approaches. Prentice Hall, 2005.
[3] M. Abramovici, E.J. Marinissen, M. Ricchetti, and B. West, "Suggested Terminology Standard for Silicon Debug and Diagnosis," Proc. IEEE Int'l Silicon Debug and Diagnosis Workshop (SDD), pp. 1-6, Nov. 2005.
[4] J.M. Soden and R.E. Anderson, "IC Failure Analysis: Techniques and Tools for Quality and Reliability Improvement," Proc. IEEE, vol. 81, no. 5, pp. 703-715, May 1993.
[5] R. Livengood and D. Medeiros, "Design for (Physical) Debug for Silicon Microsurgery and Probing of Flip-Chip Packaged Integrated Circuits," Proc. IEEE Int'l Test Conf. (ITC), pp. 877-882, Sept. 1999.
[6] R. Desplats, F. Beaudoin, P. Perdu, N. Natara, T. Lundquist, and K. Shah, "Fault Localization Using Time Resolved Photon Emission and STIL Waveforms," Proc. IEEE Int'l Test Conf. (ITC), pp. 254-263, Oct. 2003.
[7] M. Paniccia, T. Eiles, V.R.M. Rao, and W.M. Yee, "Novel Optical Probing Technique for Flip Chip Packaged Microprocessors," Proc. IEEE Int'l Test Conf. (ITC), pp. 740-747, Oct. 1998.
[8] D.P. Vallett, "IC Failure Analysis: The Importance of Test and Diagnostics," IEEE Design and Test of Computers, vol. 14, no. 3, pp. 76-82, July 1997.
[9] Y.-J. Kwon, B. Mathew, and H. Hao, "FakeFault: A Silicon Debug Software Tool for Microprocessor Embedded Memory Arrays," Proc. IEEE Int'l Test Conf. (ITC), pp. 727-732, Oct. 1998.
[10] X. Gu, W. Wang, K. Li, H. Kim, and S. Chung, "Re-using DFT Logic for Functional and Silicon Debugging Test," Proc. IEEE Int'l Test Conf. (ITC), pp. 648-656, Oct. 2002.
[11] M.E. Levitt, S. Nori, S. Narayanan, G.P. Grewal, L. Youngs, A. Jones, G. Billus, and S. Paramanandam, "Testability, Debuggability, and Manufacturability Features of the UltraSPARC-I Microprocessor," Proc. IEEE Int'l Test Conf. (ITC), pp. 157-166, Oct. 1995.
[12] B. Vermeulen, S. Oostdijk, and F. Bouwman, "Test and Debug Strategy of the PNX8525 NexperiaTM Digital Video Platform System Chip," Proc. IEEE Int'l Test Conf. (ITC), pp. 121-130, Oct. 2001.
[13] B. Vermeulen, T. Waayers, and S.K. Goel, "Core-Based Scan Architecture for Silicon Debug," Proc. IEEE Int'l Test Conf. (ITC), pp. 638-647, Oct. 2002.
[14] K. van Kaam, B. Vermeulen, and H. Bergveld, "Test and Debug Features of the RTO7 Chip," Proc. IEEE Int'l Test Conf. (ITC), pp. 274-283, Oct. 2005.
[15] R. Datta, A. Sebastine, and J.A. Abraham, "Delay Fault Testing and Silicon Debug Using Scan Chains," Proc. IEEE European Test Symp. (ETS), pp. 46-51, May 2004.
[16] D. Josephson, S. Poehhnan, and V. Govan, "Debug Methodology for the McKinley Processor," Proc. IEEE Int'l Test Conf. (ITC), pp. 451-460, Oct. 2001.
[17] C. Pyron, R. Bangalore, D. Belete, J. Goertz, A. Razdan, and D. Younger, "Silicon Symptoms to Solutions: Applying Design for Debug Techniques," Proc. IEEE Int'l Test Conf. (ITC), pp. 664-672, Oct. 2002.
[18] H. Balachandran, K. Butler, and N. Simpson, "Facilitating Rapid First Silicon Debug," Proc. IEEE Int'l Test Conf. (ITC), pp. 628-637, Oct. 2002.
[19] IEEE JTAG 1149.1-2001 Std., IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE CS, 2001.
[20] B. Vermeulen, M.Z. Urfianto, and S.K. Goel, "Automatic Generation of Breakpoint Hardware for Silicon Debug," Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 514-517, June 2004.
[21] P. Dahlgren, P. Dickinson, and I. Parulkar, "Latch Divergency in Microprocessor Failure Analysis," Proc. IEEE Int'l Test Conf. (ITC), pp. 755-763, Oct. 2003.
[22] O. Caty, P. Dahlgren, and I. Bayraktaroglu, "Microprocessor Silicon Debug Based on Failure Propagation Tracing," Proc. IEEE Int'l Test Conf. (ITC), pp. 284-293, Oct. 2005.
[23] D. Josephson, "The Manic Depression of Microprocessor Debug," Proc. IEEE Int'l Test Conf. (ITC), pp. 657-663, Oct. 2002.
[24] D. Josephson and B. Gottlieb, "The Crazy Mixed up World of Silicon Debug," Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp. 665-670, Oct. 2004.
[25] B. Vermeulen and S.K. Goel, "Design for Debug: Catching Design Errors in Digital Chips," IEEE Design and Test of Computers, vol. 19, no. 3, pp. 35-43, May 2002.
[26] K. Morris, "On-Chip Debugging—Built-in Logic Analyzers on Your FPGA," J. FPGA and Structured ASIC, vol. 2, no. 3, Jan. 2004.
[27] R. Leatherman and N. Stollon, "An Embedded Debugging Architecture for SoCs," IEEE Potentials, vol. 24, no. 1, pp. 12-16, Feb. 2005.
[28] C. MacNamee and D. Heffernan, "Emerging On-Chip Debugging Techniques for Real-Time Embedded Systems," IEE Computing & Control Eng. J., vol. 11, no. 6, pp. 295-303, Dec. 2000.
[29] Y. Huang and W.-T. Cheng, "Using Embedded Infrastructure IP for SOC Post-Silicon Verification," Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 674-677, June 2003.
[30] A. Mayer, H. Siebert, and K. McDonald-Maier, "Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs," Proc. Conf. Design, Automation, and Test in Europe (DATE), pp. 148-152, Mar. 2005.
[31] A. Swaine and J. Horley, "Summary of New Features in ETMv3," http://www.arm.com/products/solutionsETM.html , 2005.
[32] A. Hopkins and K. McDonald-Maier, "Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores," IEEE Trans. Computers, vol. 55, no. 2, pp. 174-184, Feb. 2006.
[33] S.R. Sarangi, A. Tiwari, and J. Torrellas, "Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware," Proc. IEEE Int'l Symp. Microarchitecture (ISMICRO), pp. 26-37, 2006.
[34] B. Quinton and S. Wilton, "Post-Silicon Debug Using Programmable Logic Cores," Proc. IEEE Int'l Conf. Field-Programmable Technology (ICFPT), pp. 241-248, Dec. 2005.
[35] Y.-C. Hsu, F. Tsai, W. Jong, and Y.-T. Chang, "Visibility Enhancement for Silicon Debug," Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 13-18, July 2006.
[36] Altera Verification Tool, "SignalTap II Embedded Logic Analyzer," http://www.altera.com/products/software/ products/ quartus2/verification/signaltap2 sig-index.html, 2008.
[37] Xilinx Verification Tool, "ChipScope Pro," http://www.xilinx. com/ise/optional_prod cspro.html, 2008.
[38] Synplicity Verification Tool, "Identify," http://www.synplicity. com/products/identify index.html, 2008.
[39] IEEE Industry Standards and Technology Organization, The Nexus 5001 Forum Standard for a Global Embedded Processor Debug Interface, http:/www.nexus5001.org, 2003.
[40] A. Hopkins and K. McDonald-Maier, "Debug Support for Complex Systems On-Chip: A Review," IEE Proc. Computers and Digital Techniques, vol. 153, no. 4, pp. 197-207, July 2006.
[41] H.F. Ko and N. Nicolici, "Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation," Proc. Conf. Design, Automation, and Test in Europe (DATE), pp. 1298-1303, Mar. 2008.
[42] E. Anis and N. Nicolici, "On Using Lossless Compression of Debug Data in Embedded Logic Analysis," Proc. IEEE Int'l Test Conf. (ITC), pp. 1-10, Oct. 2007.
[43] S. Sarangi, B. Greskamp, and J. Torrellas, "CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging," Proc. IEEE Int'l Conf. Dependable Systems and Networks (IDSN), pp. 301-312, June 2006.
[44] I. Silas, I. Frumkin, E. Hazan, E. Mor, and G. Zobin, "System-Level Validation of the Intel Pentium M Processor," Intel Technology J., vol. 7, no. 2, pp. 37-43, May 2003.
[45] J. Ghosh-Dastidar and N.A. Touba, "A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains," Proc. IEEE VLSI Test Symp. (VTS), pp. 79-85, Apr. 2000.
[46] S. Hacker, MP3: The Definitive Guide. O'Reilly & Assoc., Inc., May 2000.

Index Terms:
Silicon debug, observation window, lossy compression.
Citation:
Ehab Anis Daoud, Nicola Nicolici, "On Using Lossy Compression for Repeatable Experiments during Silicon Debug," IEEE Transactions on Computers, vol. 60, no. 7, pp. 937-950, July 2011, doi:10.1109/TC.2010.122
Usage of this product signifies your acceptance of the Terms of Use.