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Issue No.06 - June (2011 vol.60)
pp: 896-903
George Michelogiannakis , Stanford University, Stanford
Daniel U. Becker , Stanford University, Stanford
William J. Dally , Stanford University, Stanford
ABSTRACT
With the emergence of on-chip networks, router buffer power has become a primary concern. Elastic buffer (EB) flow control utilizes existing pipeline flip-flops in the channels to implement distributed FIFOs, eliminating the need for input buffers at the routers. EB routers have been shown to be more efficient than virtual channel routers, as they do not require input buffers or complex logic for managing virtual channels and tracking credits. Wormhole routers are more comparable in terms of complexity because they also lack virtual channels. This paper compares EB and wormhole routers and explores novel hybrid designs to more closely examine the effect of design simplicity and input buffer cost. Our results show that EB routers have up to 25 percent smaller cycle time compared to wormhole and hybrid routers. Moreover, EB flow control requires 10 percent less energy to transfer a single bit through a router and offers three percent more throughput per unit energy as well as 62 percent more throughput per unit area. The main contributor to these results is the cost and delay overhead of the input buffer.
INDEX TERMS
On-chip interconnection networks, interconnection architectures.
CITATION
George Michelogiannakis, Daniel U. Becker, William J. Dally, "Evaluating Elastic Buffer and Wormhole Flow Control", IEEE Transactions on Computers, vol.60, no. 6, pp. 896-903, June 2011, doi:10.1109/TC.2010.243
REFERENCES
[1] W.J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. 38th Ann. Conf. Design Automation, 2001.
[2] Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, "A 5-GHz Mesh Interconnect for a Teraflops Processor," IEEE Micro, vol. 27, no. 5, pp. 51-61, Sept./Oct. 2007.
[3] M.B. Taylor, W. Lee, J. Miller, D. Wentzlaff, I. Bratt, B. Greenwald, H. Hoffmann, P. Johnson, J. Kim, J. Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, and A. Agarwal, "Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for Ilp and Streams," ISCA '04: Proc. 31st Ann. Int'l Symp. Computer Architecture, pp. 2-13, 2004.
[4] W.J. Dally, "Virtual-Channel Flow Control," IEEE Trans. Parallel and Distributed Systems, vol. 3, no. 2, pp. 194-205, Mar. 1992.
[5] P. Gratz, C. Kim, R. McDonald, S. Keckler, and D. Burger, "Implementation and Evaluation of On-Chip Network Architectures," Proc. Int'l Conf. Computer Design (ICCD '06), pp. 477-484, 2006.
[6] C. Gómez, M.E. Gómez, P. López, and J. Duato, "Reducing Packet Dropping in a Bufferless NoC," Proc. 14th Int'l Euro-Par Conf. Parallel Processing, 2008.
[7] T. Moscibroda and O. Mutlu, "A Case for Bufferless Routing in On-Chip Networks," ACM SIGARCH Computer Architecture News, vol. 37, no. 3, pp. 196-207, 2009.
[8] J. Liu, L.-R. Zheng, and H. Tenhunen, "A Guaranteed-Throughput Switch for Network-on-Chip," Proc. Int'l Symp. System-on-Chip, pp. 31-34, 2003.
[9] J. Duato, P. Lopez, F. Silla, and S. Yalamanchili, "A High Performance Router Architecture for Interconnection Networks," Proc. Int'l Conf. Parallel Processing, vol. 1, pp. 61-68, citeseer.ist.psu.eduduato96high.html, 1996.
[10] G. Michelogiannakis, D. Pnevmatikatos, and M. Katevenis, "Approaching Ideal NoC Latency with Pre-Configured Routes," NOCS '07: Proc. First Int'l Symp. Networks-on-Chip, pp. 153-162, 2007.
[11] A. Kumar, L.-S. Peh, P. Kundu, and N.K. Jha, "Express Virtual Channels: Towards the Ideal Interconnection Fabric," Proc. 34th Ann. Int'l Symp. Computer Architecture, pp. 150-161, 2007.
[12] G. Michelogiannakis, J. Balfour, and W.J. Dally, "Elastic Buffer Flow Control for On-Chip Networks," HPCA '09: Proc. 15th Int'l Symp. High-Performance Computer Architecture, pp. 151-162, 2009.
[13] A. Pullini, F. Angiolini, D. Bertozzi, and L. Benini, "Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes," SBCCI '05: Proc. 18th Ann. Symp. Integrated Circuits and System Design, pp. 224-229, 2005.
[14] G. Michelogiannakis and W.J. Dally, "Router Designs for Elastic Buffer On-Chip Networks," SC '09: Proc. Conf. High Performance Computing Networking, Storage and Analysis, pp. 1-10, 2009.
[15] M. Galles, "Spider: A High-Speed Network Interconnect," IEEE Micro, vol. 17, no. 1, pp. 34-39, Jan./Feb. 1997.
[16] L. Ni and P. McKinley, "A Survey of Wormhole Routing Techniques in Direct Networks," pp. 492-506, 2000.
[17] A. Banerjee, R. Mullins, and S. Moore, "A Power and Energy Exploration of Network-on-Chip Architectures," NOCS '07: Proc. First Int'l Symp. Networks-on-Chip, pp. 163-172, 2007.
[18] W.J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, Inc., 2003.
[19] A.B. Kahng, B. Li, L.-S. Peh, and K. Samadi, "Orion 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration," Proc. 46th Ann. Conf. Design Automation, pp. 423-428, 2009.
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