Issue No.06 - June (2011 vol.60)
George Michelogiannakis , Stanford University, Stanford
Daniel U. Becker , Stanford University, Stanford
William J. Dally , Stanford University, Stanford
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.243
With the emergence of on-chip networks, router buffer power has become a primary concern. Elastic buffer (EB) flow control utilizes existing pipeline flip-flops in the channels to implement distributed FIFOs, eliminating the need for input buffers at the routers. EB routers have been shown to be more efficient than virtual channel routers, as they do not require input buffers or complex logic for managing virtual channels and tracking credits. Wormhole routers are more comparable in terms of complexity because they also lack virtual channels. This paper compares EB and wormhole routers and explores novel hybrid designs to more closely examine the effect of design simplicity and input buffer cost. Our results show that EB routers have up to 25 percent smaller cycle time compared to wormhole and hybrid routers. Moreover, EB flow control requires 10 percent less energy to transfer a single bit through a router and offers three percent more throughput per unit energy as well as 62 percent more throughput per unit area. The main contributor to these results is the cost and delay overhead of the input buffer.
On-chip interconnection networks, interconnection architectures.
George Michelogiannakis, Daniel U. Becker, William J. Dally, "Evaluating Elastic Buffer and Wormhole Flow Control", IEEE Transactions on Computers, vol.60, no. 6, pp. 896-903, June 2011, doi:10.1109/TC.2010.243