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| Sherief Reda, Ryan J. Cochran, Abdullah Nazma Nowroz, "Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques," IEEE Transactions on Computers, vol. 60, no. 6, pp. 841-851, June, 2011. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.2011.45, author = {Sherief Reda and Ryan J. Cochran and Abdullah Nazma Nowroz}, title = {Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques}, journal ={IEEE Transactions on Computers}, volume = {60}, number = {6}, issn = {0018-9340}, year = {2011}, pages = {841-851}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2011.45}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques IS - 6 SN - 0018-9340 SP841 EP851 EPD - 841-851 A1 - Sherief Reda, A1 - Ryan J. Cochran, A1 - Abdullah Nazma Nowroz, PY - 2011 KW - Thermal KW - power KW - characterization KW - sensors KW - tracking KW - hot spot KW - infrared imaging. VL - 60 JA - IEEE Transactions on Computers ER - | |||
[1] S. Borkar, "Thousand Core Chips—A Technology Perspective," Proc. Design Automation Conf., pp. 746-749, May 2007.
[2] D. Brooks, R. Dick, R. Joseph, and L. Shang, "Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors," IEEE Micro, vol. 27, no. 3, pp. 49-62, May/June 2007.
[3] D. Brooks and M. Martonosi, "Dynamic Thermal Management for High-Performance Microprocessors," Proc. High Performance Computer Architecture, pp. 171-182, 2001.
[4] D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," Proc. Int'l Symp. Computer Architecture, pp. 83-94, 2000.
[5] A. Coskun, T. Rosing, K. Whisnant, and K. Gross, "Temperature-Aware MPSoC Scheduling for Reducing Hot Spots and Gradients," Proc. Asia and South Pacific Design Automation Conf., pp. 49-54, http://portal.acm.orgcitation.cfm?id=1356802.1356815 , 2008.
[6] A.K. Coskun, T.S. Rosing, and K.C. Gross, "Proactive Temperature Management in MPSoCs," Proc. Int'l Symp. Low Power Electronics and Design, pp. 165-170, 2008.
[7] J. Donald and M. Martonosi, "Techniques for Multicore Thermal Management: Classification and New Exploration," Proc. Int'l Symp. Computer Architecture, pp. 78-88, 2006.
[8] A. Eivril and M. Magdon-Ismail, "On Selecting a Maximum Volume Sub-Matrix of a Matrix and Related Problems," Theoretical Computer Science, vol. 410, pp. 4801-4811, 2009.
[9] M.R. Garey and D.S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, first ed., W.H. Freeman and Company, 1979.
[10] H. Hamann, A. Weger, J. Lacey, Z. Hu, and P. Bose, "Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 56-65, Jan. 2007.
[11] H. Hanson, S.W. Keckler, S. Ghiasi, K. Rajamani, F. Rawson, and J. Rubio, "Thermal Response to DVFS: Analysis with an Intel Pentium M," Proc. Int'l Symp. Low Power Electronics and Design, pp. 219-224, 2007.
[12] S. Heo, K. Barr, and K. Asanović, "Reducing Power Density through Activity Migration," Proc. Int'l Symp. Low Power Electronics and Design, pp. 217-222, 2003.
[13] C. Hsieh, C. Wu, F. Jih, and T. Sun, "Focal-Plane-Arrays and CMOS Readout Techniques of Infrared Imaging Systems," IEEE Trans. Circuits and Systems for Video Technology, vol. 7, no. 4, pp. 594-605, Aug. 1997.
[14] W. Huan, M.R. Stan, K. Sankaranarayanan, R.J. Ribando, and K. Skadron, "Many-Core Design from a Thermal Perspective," Proc. Design Automation Conf., pp. 746-749, 2008.
[15] W. Huang, K. Skadron, S. Gurumurthi, R.J. Ribando, and M.R. Stan, "Differentiating the Roles of IR Measurement and Simulation for Power and Temperature-Aware Design," Proc. Int'l Symp. Performance Analysis of Systems and Software, pp. 1-10, 2009.
[16] W. Huang, M. Stan, K. Skadron, and K. Sankaranarayanan, "Compact Thermal Modeling for Temperature-Aware Design," Proc. Design Automation Conf., pp. 887-883, http://portal.acm.org citation.cfm?id=996566.996800 , 2004.
[17] H. Jung and M. Pedram, "A Stochastic Local Hot Spot Alerting Technique," Proc. Asia and South Pacific Design Automation Conf., pp. 468-473, 2008.
[18] H. Jung, P. Rong, and M. Pedram, "Stochastic Modeling of a Thermally-Managed Multi-Core System," Proc. Design Automation Conf., pp. 728-733, http://ieeexplore.ieee.org/searchsrchabstract.jsp?arnumber=4555915&isnumber=4555759& punumber=4547421&k2dockey=4555915@ieeecnfs , 2008.
[19] M. Kadin and S. Reda, "Frequency and Voltage Planning for Multi-Core Processors under Thermal Constraints," Proc. Int'l Conf. Computer Design, pp. 463-470, 2008.
[20] O. Khan and S. Kundu, "A Framework for Predictive Dynamic Temperature Management of Microprocessor Systems," Proc. Int'l Conf. Computer-Aided Design, pp. 258-263, http://portal.acm.orgcitation.cfm?id=1509520 , Jan. 2008.
[21] A. Kumar, L. Shang, L.-S. Peh, and N.K. Jha, "HybDTM: A Coordinated Hardware-Software Approach for Dynamic Thermal Management," Proc. Design Automation Conf., pp. 548-553, 2006.
[22] B. Lee, K. Chung, B. Koo, and N. Eum, "Thermal Sensor Allocation and Placement for Reconfigurable Systems," ACM Trans. Design Automation of Electronic Systems, vol. 14, no. 4, pp. 50:1-50:23, 2009.
[23] K. Lee, K. Skadron, and W. Huang, "Analytical Model for Sensor Placement on Microprocessors," Proc. Int'l Conf. Computer Design, pp. 24-30, 2005.
[24] K.-J. Lee and K. Skadron, "Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors," Proc. 19th IEEE Int'l Parallel and Distributed Processing Symp., 2005.
[25] S.-C. Lin and K. Banerjee, "Cool Chips: Opportunities and Implications for Power and Thermal Management," IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 245-255, Jan. 2008.
[26] J. Long, S. Memik, G. Memik, and R. Mukherjee, "Thermal Monitoring Mechanisms for Chip Multiprocessors," ACM Trans. Architecture and Code Optimization, vol. 5, no. 2, pp. 9:1-9:23, 2008.
[27] R. McGowen, C. Poirier, C. Bostak, and J. Ignowski, "Power and Temperature Control on a 90-nm Itanium Family Processor," IEEE Trans. Solid-State Circuits, vol. 41, no. 1, pp. 229-237, http://ieeexplore.ieee.org/xplsabs_all.jsp?arnumber=1564363 , Jan. 2006.
[28] S. Memik, R. Mukherjee, M. Ni, and J. Long, "Optimizing Thermal Sensor Allocation for Microprocessors," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 3, pp. 516-527, Mar. 2008.
[29] F.J. Mesa-Martinez, E. Ardestani, and J. Renau, "Characterizing Processor Thermal Behavior," Proc. Architectural Support for Programming Languages and Operating Systems, pp. 193-204, 2010.
[30] F.J. Mesa-Martinez, M. Brown, J. Nayfach-Battilana, and J. Renau, "Measuring Performance, Power, and Temperature from Real Processors," Proc. Int'l Symp. Computer Architecture, pp. 1-10, 2007.
[31] R. Mukherjee and S. Memik, "Physical Aware Frequency Selection for Dynamic Thermal Management in Multi-Core Systems," Proc. Int'l Conf. Computer-Aided Design, pp. 547-552, 2006.
[32] R. Mukherjee and S. Memik, "Systematic Temperature Sensor Allocation and Placement for Microprocessors," Proc. Design Automation Conf., pp. 542-547, 2006.
[33] R. Mukherjee, S. Mondal, and S.O. Memik, "Thermal Sensor Allocation and Placement for Reconfigurable Systems," Proc. Int'l Conf. Computer-Aided Design, pp. 437-442, 2006.
[34] S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. Boyd, and G.D. Micheli, "Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization," Proc. Fifth IEEE/ACM Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 111-116, 2007.
[35] A.N. Nowroz, R. Cochran, and S. Reda, "Thermal Monitoring of Real Processors: Techniques for Sensor Allocation and Full Characterization," Proc. Design Automation Conf., pp. 56-61, 2010.
[36] M. Pedram and S. Nazarin, "Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods," Proc. IEEE, vol. 94, no. 8, pp. 1487-1501, Aug. 2006.
[37] M.D. Powell, M. Gomaa, and T.N. Vijaykumar, "Heat-and-Run: Leveraging SMT and CMP to Manage Power Density through the Operating System," Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems, pp. 260-270, 2004.
[38] R. Cochran and S. Reda, "Spectral Techniques for High-Resolution Thermal Characterization with Limited Sensor Data," Proc. Design Automation Conf., pp. 478-483, 2009.
[39] A. Rogalski and K. Chrzanowski, "Infrared Devices and Techniques," Opto-Electronics Rev., vol. 10, no. 2, pp. 111-136, 2002.
[40] E. Rotem, J. Hermerding, C. Aviad, and C. Harel, "Temperature Measurement in the Intel Core Duo Processor," Proc. Int'l Workshop Thermal Investigations of ICs, pp. 23-27, 2006.
[41] K. Skadron, "Hybrid Architectural Dynamic Thermal Management," Proc. Design, Automation and Test in Europe Conf., pp. 10-15, 2004.
[42] G. Strang, Computational Science and Engineering, first ed., Wellesly-Cambridge Press, 2007.
[43] J. Winter and D. Albonesi, "Addressing Thermal Nonuniformity in SMT Workloads," ACM Trans. Architecture and Code Optimization, vol. 5, no. 1, pp. 4:1-4:28, http://portal.acm.orgcitation.cfm? id=1369396.1369400 , 2008.
[44] J. Yang, X. Zhou, M. Chrobak, Y. Zhang, and L. Jin, "Dynamic Thermal Management through Task Scheduling," Proc. Int'l Symp. Performance Analysis of Systems and Software, pp. 191-201, http://ieeexplore.ieee.org/searchsrchabstract.jsp?arnumber=4510751& isn umber=4510727&punumber=4498398&k2dockey= 4510751@ieeecnfs , 2008.
[45] S. Zhang and K.S. Chatha, "Approximation Algorithm for the Temperature-Aware Scheduling Problem," Proc. Int'l Conf. Computer-Aided Design, pp. 281-288, 2007.
[46] Y. Zhang, A. Srivastava, and M. Zahran, "On-Chip Sensor-Driven Efficient Thermal Profile Estimation Algorithms," ACM Trans. Design Automation of Electronic Systems, vol. 15, no. 3, p. 25:1, 2010.
[47] C. Zhu, Z. Gu, L. Shang, R. Dick, and R. Joseph, "Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1479-1492, http://ieeexplore.ieee.org/xplsabs_all.jsp?arnumber=4527121 , Aug. 2008.

