Issue No.06 - June (2011 vol.60)
Yi-Jung Chen , National Taiwan University, Taipei
Chia-Lin Yang , National Taiwan University, Taipei
Jaw-Wei Chi , National Taiwan University, Taipei
Jian-Jia Chen , Karlsruhe Institute of Technology (KIT), Germany
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2011.44
Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Existing leakage reduction techniques for hard real-time systems utilize slack to turn off a CPU completely. However, turning on/off a processor involves high performance and energy overheads. Hence, a hard real-time system is very likely to have unutilized slack if only the CPU shutdown technique is used to reduce leakage. Architectural-level shutdown techniques in all instances have a much lower overheads than turning off a CPU; therefore, they can be utilized in a hard real-time system to further reduce CPU leakage. However, existing architecture-level shutdown techniques cause unpredictable performance degradation thereby unsuitable for a hard real-time system that must meet the timing constraint in all cases. This paper is the first attempt to bridge this gap. This paper focuses on cache leakage reduction and proposes the first Timing-Aware Cache Leakage Control (TACLC) mechanism. TACLC exploits system slack to turn cache lines into low-leakage states provided that the timing constraint is met. The experimental results demonstrate that TACLC effectively utilizes system slack to reduce cache leakage. For systems with low CPU utilization, TACLC achieves comparable leakage reduction to the leakage control policy that aggressively turns cache lines into low-leakage modes while neglecting the timing constraint.
Cache, leakage control, hard real-time systems, energy management.
Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen, "TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems", IEEE Transactions on Computers, vol.60, no. 6, pp. 767-782, June 2011, doi:10.1109/TC.2011.44