This Article 
 Bibliographic References 
 Add to: 
Energy Reduction in Consolidated Servers through Memory-Aware Virtual Machine Scheduling
April 2011 (vol. 60 no. 4)
pp. 552-564
Jae-Wan Jang, Korea Advanced Institute of Science and Technology (KAIST), Daejeon
Myeongjae Jeon, Rice University, Houston
Hyo-Sil Kim, Korea Advanced Institute of Science and Technology (KAIST), Daejeon
Heeseung Jo, Korea Advanced Institute of Science and Technology (KAIST), Daejeon
Jin-Soo Kim, Sungkyunkwan University, Suwon
Seungryoul Maeng, Korea Advanced Institute of Science and Technology (KAIST), Daejeon
Increasing energy consumption in server consolidation environments leads to high maintenance costs for data centers. Main memory, no less than processor, is a major energy consumer in this environment. This paper proposes a technique for reducing memory energy consumption using virtual machine scheduling in multicore systems. We devise several heuristic scheduling algorithms by using a memory power simulator, which we designed and implemented. We also implement the biggest cover set first (BCSF) scheduling algorithm in the working server system. Through extensive simulation and implementation experiments, we observe the effectiveness of the memory-aware virtual machine scheduling in saving memory energy. In addition, we find out that power-aware memory management is essential to reduce the memory energy consumption.

[1] C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T.W. Keller, "Energy Management for Commercial Servers," Computer, vol. 36, no. 12, pp. 39-48, Dec. 2003.
[2] R. Bianchini and R. Rajamony, "Power and Energy Management for Server Systems," Computer, vol. 37, no. 11, pp. 68-74, Nov. 2004.
[3] D. Meisner, B.T. Gold, and T.F. Wenisch, "PowerNap: Eliminating Server Idle Power," Proc. 14th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, pp. 205-216, 2009.
[4] VMware, "Server Consolidation Overview, Building a Virtual Infrastructure," consolidation consolidate.html, 2009.
[5] Micron Technology, Inc., DDR3 SDRAM, http:/www.micron. com, 2009.
[6] "DDR3 SDRAM MT41J256M4—32 Meg × 4 × 8 Banks," Micron Technology, Inc., 2006.
[7] "1.35V/1.5V Registering Clock Driver with Parity Test and Quad Chip Select (SSTE32882HLB)," Integrated Device Tech nology, 2006.
[8] K. Fraser, S. Hand, R. Neugebauer, I. Pratt, A. Warfield, and M. Williamson, "Safe Hardware Access with the Xen Virtual Machine Monitor," Proc. First Workshop Operating System and Architectural Support for the On Demand IT InfraStructure, 2004.
[9] VMware, "ESX Server—Best Practices Using VMware Virtual SMP," white paper, practices.pdf , 2005.
[10] L. Cherkasova, D. Gupta, and A. Vahdat, "Comparison of the Three CPU Schedulers in Xen," ACM SIGMETRICS Performance Evaluation Rev., vol. 35, no. 2, pp. 42-51, 2007.
[11] D. Ongaro, A.L. Cox, and S. Rixner, "Scheduling I/O in Virtual Machine Monitors," Proc. Conf. Virtual Execution Environments (VEE), pp. 1-10, 2008.
[12] V. Delaluz, A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan, and M.J. Irwin, "Scheduler-Based DRAM Energy Management," Proc. 39th Ann. Design Automation Conf. (DAC), pp. 697-702, 2002.
[13] J.-W. Jang, M. Jeon, H.-S. Kim, H. Jo, J.-S. Kim, and S. Maeng, "NP-Completeness of Memory-Aware Virtual Machine Scheduling Problem," Technical Report CS-TR-2009-321, Computer Science Dept., KAIST, 2009.
[14] C. Amza, A. Chanda, A. Cox, S. Elnikety, R. Gil, K. Rajamani, W. Zwaenepoel, E. Cecchet, and J. Marguerite, "Specification and Implementation of Dynamic Web Site Benchmarks," Proc. IEEE Workshop Workload Characterization (WWC), pp. 3-13, 2002.
[15] T. Richardson, Q. Stafford-fraser, K.R. Wood, and A. Hopper, "Virtual Network Computing," IEEE Internet Computing, vol. 2, no. 1, pp. 33-38, Jan./Feb. 1998.
[16] J.R. Santos, Y. Turner, G.J. Janakiraman, and I. Pratt, "Bridging the Gap between Software and Hardware Techniques for I/O Virtualization," Proc. USENIX Ann. Technical Conf., pp. 29-42, 2008.
[17] C.A. Waldspurger, "Memory Resource Management in VMware ESX Server," ACM SIGOPS Operating Systems Rev., vol. 36, pp. 181-194, 2002.
[18] D. Gupta, S. Lee, M. Vrable, S. Savage, A.C. Snoeren, G. Varghese, G.M. Voelker, and A. Vahdat, "Difference Engine: Harnessing Memory Redundancy in Virtual Machines," Proc. In 8th USENIX Symp. Operating Systems Design and Implementation (OSDI), 2008.
[19] H. Huang, P. Pillai, and K.G. Shin, "Design and Implementation of Power-Aware Virtual Memory," Proc. USENIX Ann. Technical Conf., 2003.
[20] M. Lee, E. Seo, J. Lee, and J.-S. Kim, "PABC: Power-Aware Buffer Cache Management for Low Power Consumption," IEEE Trans. Computers, vol. 56, no. 4, pp. 488-501, Apr. 2007.

Index Terms:
DRAM energy, virtual machine, scheduling, multicore processor.
Jae-Wan Jang, Myeongjae Jeon, Hyo-Sil Kim, Heeseung Jo, Jin-Soo Kim, Seungryoul Maeng, "Energy Reduction in Consolidated Servers through Memory-Aware Virtual Machine Scheduling," IEEE Transactions on Computers, vol. 60, no. 4, pp. 552-564, April 2011, doi:10.1109/TC.2010.82
Usage of this product signifies your acceptance of the Terms of Use.