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Issue No.03 - March (2011 vol.60)

pp: 335-345

Ningde Xie , Rensselaer Polytechnic Institute, Troy

Guiqiang Dong , Rensselaer Polytechnic Institute, Troy

Tong Zhang , Rensselaer Polytechnic Institute, Troy

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.150

ABSTRACT

Lossless data compression for data storage has become less popular as mass data storage systems are becoming increasingly cheap. This leaves many files stored on mass data storage media uncompressed although they are losslessly compressible. This paper proposes to exploit the lossless compressibility of those files to improve the underlying storage system performance metrics such as energy efficiency and access speed, other than saving storage space as in conventional practice. The key idea is to apply runtime lossless data compression to enable an opportunistic use of a stronger error correction code (ECC) with more coding redundancy in data storage systems, and trade such opportunistic extra error correction capability to improve other system performance metrics in the runtime. Since data storage is typically realized in the unit of equal-sized sectors (e.g., 512 B or 4 KB user data per sector), we only apply this strategy to each individual sector independently in order to be completely transparent to the firmware, operating systems, and users. Using low-density parity check (LDPC) code as ECC in storage systems, this paper quantitatively studies the effectiveness of this design strategy in both hard disk drives and NAND flash memories. For hard disk drives, we use this design strategy to reduce average hard disk drive read channel signal processing energy consumption, and results show that up to 38 percent read channel energy saving can be achieved. For NAND flash memories, we use this design strategy to improve average NAND flash memory write speed, and results show that up to 36 percent write speed improvement can be achieved for 2 bits/cell NAND flash memories.

INDEX TERMS

Data storage, lossless compression, hard disk drive, NAND flash memory, error correction code.

CITATION

Ningde Xie, Guiqiang Dong, Tong Zhang, "Using Lossless Data Compression in Data Storage Systems: Not for Saving Space",

*IEEE Transactions on Computers*, vol.60, no. 3, pp. 335-345, March 2011, doi:10.1109/TC.2010.150REFERENCES

- [1] K. Sayood,
Introduction to Data Compression, second ed. Morgan Kaufmann, 2000.- [2] R. Wood, Y. Sonobe, Z. Jin, and B. Wilson, "Perpendicular Recording: The Promise and the Problems,"
J. Magnetism and Magnetic Materials, vol. 235, pp. 1-9, Oct. 2001.- [3] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to Flash Memory,"
Proc. IEEE, vol. 91, no. 4, pp. 489-502, Apr. 2003.- [4] R.G. Gallager,
Low-Density Parity-Check Codes. MIT Press, 1963.- [5] D.J.C. MacKay, "Good Error-Correcting Codes Based on Very Sparse Matrices,"
IEEE Trans. Information Theory, vol. 45, no. 2, pp. 399-431, Mar. 1999.- [6] T. Richardson, A. Shokrollahi, and R. Urbanke, "Design of Capacity-Approaching Low-Density Parity-Check Codes,"
IEEE Trans. Information Theory, vol. 47, no. 2, pp. 619-637, Feb. 2001.- [7] S. Lin and D.J. Costello,
Error Control Coding: Fundamentals and Applications, second ed. Prentice Hall, 2004.- [8] R.D. Cideciyan, E. Eleftheriou, and T. Mittelholzer, "Perpendicular and Longitudinal Recording: A Signal-Processing and Coding Perspective,"
IEEE Trans. Magnetics, vol. 38, no. 4, pp. 1698-1704, July 2002.- [9] E.F. Haratsch and Z.A. Keirn, "Digital Signal Processing in Read Channels,"
Proc. IEEE Custom Integrated Circuits Conf., pp. 683-690, Sept. 2005.- [10] T. Hara, "A 146-mm$^2$ 8-Gb Multi-Level NAND Flash Memory with 70-nm CMOS Technology,"
IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 161-169, Jan. 2006.- [11] Y. Li, "A 16Gb 3b/Cell NAND Flash Memory in 56nm with 8MB/s Write Rate,"
Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC), pp. 506-632, Feb. 2008.- [12] Y. Li, "A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology with 8 MB/s Write Rate,"
IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 195-207, Jan. 2009.- [13] C. Trinh, "A 5.6MB/s 64Gb 4b/Cell NAND Flash Memory in 43nm CMOS,"
Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC), pp. 246-247, Feb. 2009.- [14] L. Sun, H. Song, and B.V.K.V. Kumar, "Error Floor Investigation and Girth Optimization for Certain Types of Low-Density Parity Check Codes,"
Proc. IEEE Int'l Conf. Acoustics, Speech, and Signal Processing, pp. 1101-1104, Mar. 2005.- [15] L. Sun, H. Song, B.V.K.V. Kumar, and Z. Keirn, "Field-Programmable Gate-Array-Based Investigation of the Error Floor of Low-Density Parity Check Codes for Magnetic Recording Channels,"
IEEE Trans. Magnetics, vol. 41, no. 10, pp. 2983-2985, Oct. 2005.- [16] X. Hu and B.V.K.V. Kumar, "Evaluation of Low-Density Parity-Check Codes on Perpendicular Magnetic Recording Model,"
IEEE Trans. Magnetics, vol. 43, no. 2, pp. 727-732, Feb. 2007.- [17] S. Jeon, X. Hu, L. Sun, and B.V.K.V. Kumar, "Performance Evaluation of Partial Response Targets for Perpendicular Recording Using Field Programmable Gate Arrays,"
IEEE Trans. Magnetics, vol. 43, no. 6, pp. 2259-2261, June 2007.- [18] X. Hu, B.V.K.V. Kumar, Z. Li, and R. Barndt, "Error Floor Estimation of Long LDPC Codes on Partial Response Channels,"
Proc. Global Telecomm. Conf. (GLOBECOM), pp. 259-264, Nov. 2007.- [19] N. Xie, W. Xu, T. Zhang, E.F. Haratsch, and J. Moon, "Concatenated LDPC and BCH Coding System for Magnetic Recording Read Channel with 4K-Byte Sector Format,"
IEEE Trans. Magnetics, vol. 44, no. 12, pp. 4784-4789, Dec. 2008.- [20]
LDPC Technology Comes to Disk-Read Channels, http://www.edn. com/articleCA6670958.html , July 2009.- [21] F.R. Kschischang, B.J. Frey, and H.-A. Loeliger, "Factor Graphs and the Sum-Product Algorithm,"
IEEE Trans. Information Theory, vol. 47, no. 2, pp. 498-519, Feb. 2001.- [22] R. Wood, "The Feasibility of Magnetic Recording at 1 Terabit Per Square Inch,"
IEEE Trans. Magnetics, vol. 36, no. 1, pp. 36-42, Jan. 2000.- [23] E.M. Kurtas, M.F. Erden, and X. Yang, "Future Read Channel Technologies and Challenges for High Density Data Storage Applications,"
Proc. IEEE Int'l Conf. Acoustics, Speech, and Signal Processing (ICASSP), pp. v/737-v/740, Mar. 2005.- [24] S.I. Iwasaki and Y. Nakamura, "An Analysis for the Magnetization Mode for High Density Magnetic Recording,"
IEEE Trans. Magnetics, vol. MAG-13, no. 5, pp. 1272-1277, Sept. 1977.- [25] W. Cain, A. Payne, M. Baldwinson, and R. Hempstead, "Challenges in the Practical Implementation of Perpendicular Magnetic Recording,"
IEEE Trans. Magnetics, vol. 32, no. 1, pp. 97-102, Jan. 1996.- [26] J. Moon, "SNR Definition for Magnetic Recording Channels with Transition Noise,"
IEEE Trans. Magnetics, vol. 36, no. 5, pp. 3881-3883, Sept. 2000.- [27] R.D. Cideciyan, E. Eleftheriou, and T. Mittelholzer, "Perpendicular and Longitudinal Recording: A Signal-Processing and Coding Perspective,"
IEEE Trans. Magnetics, vol. 38, no. 4, pp. 1698-1704, July 2002.- [28] E. Yeo, "A 500 Mb/s Soft-Output Viterbi Decoder,"
IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1234-1241, July 2003.- [29] Z. Li, L. Chen, S. Lin, W. Fong, and P.-S. Yeh, "Efficient Encoding of Quasi-Cyclic Low-Density Parity-Check Codes,"
IEEE Trans. Comm., vol. 54, no. 1, pp. 71-81, Jan. 2006.- [30] J. Chen, A. Dholakia, E. Eleftheriou, M.P.C. Fossorier, and X.-Y. Hu, "Reduced-Complexity Decoding of LDPC Codes,"
IEEE Trans. Comm., vol. 53, no. 8, pp. 1288-1299, Aug. 2005.- [31] H. Zhong, W. Xu, N. Xie, and T. Zhang, "Area-Efficient Min-Sum Decoder Design for High-Rate Quasi-Cyclic Low-Density Parity-Check Codes in Magnetic Recording,"
IEEE Trans. Magnetics, vol. 43, no. 12, pp. 4117-4122, Dec. 2007.- [32] J. Ziv and A. Lempel, "A Universal Algorithm for Sequential Data Compression,"
IEEE Trans. Information Theory, vol. IT-23, no. 3, pp. 337-343, May 1977.- [33] L.N. Bairavasundaram, G.R. Goodson, S. Pasupathy, and J. Schindler, "An Analysis of Latent Sector Errors in Disk Drives,"
Proc. 2007 ACM SIGMETRICS, pp. 289-300, 2007.- [34] R. Zeng, "A $172\;{\rm mm}^2 \;32\;{\rm Gb}$ MLC NAND Flash Memory in 34nm CMOS,"
Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC), pp. 236-237, Feb. 2009.- [35] N. Shibata, "A 70nm 16Gb 16-Level-Cell NAND Flash Memory,"
IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 929-937, Apr. 2008.- [36] K.-T. Park, "A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories,"
IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 919-928, Apr. 2008.- [37] K. Takeuchi, T. Tanaka, and H. Nakamura, "A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories,"
IEEE J. Solid-State Circuits, vol. 31, no. 4, pp. 602-609, Apr. 1996. |