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A Real/Complex Logarithmic Number System ALU
February 2011 (vol. 60 no. 2)
pp. 202-213
ASCII Text
x 
 
Mark G. Arnold, Sylvain Collange, "A Real/Complex Logarithmic Number System ALU," IEEE Transactions on Computers, vol. 60, no. 2, pp. 202-213, February, 2011.
 
 
BibTex
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@article{ 10.1109/TC.2010.154,
author = {Mark G. Arnold and Sylvain Collange},
title = {A Real/Complex Logarithmic Number System ALU},
journal ={IEEE Transactions on Computers},
volume = {60},
number = {2},
issn = {0018-9340},
year = {2011},
pages = {202-213},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2010.154},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - A Real/Complex Logarithmic Number System ALU
IS - 2
SN - 0018-9340
SP202
EP213
EPD - 202-213
A1 - Mark G. Arnold,
A1 - Sylvain Collange,
PY - 2011
KW - Complex arithmetic
KW - logarithmic number system
KW - hardware function evaluation
KW - FPGA
KW - fast Fourier transform
KW - VHDL.
VL - 60
JA - IEEE Transactions on Computers
ER -
 
Mark G. Arnold, Lehigh University, Bethlehem
Sylvain Collange, ELIAUS, Université de Perpignan, Perpignan
The real Logarithmic Number System (LNS) offers fast multiplication but uses more expensive addition. Cotransformation and higher order table methods allow real LNS ALUs with reasonable precision on Field-Programmable Gate Arrays (FPGAs). The Complex LNS (CLNS) is a generalization of LNS, which represents complex values in log-polar form. CLNS is a more compact representation than traditional rectangular methods, reducing bus and memory cost in the FFT; however, prior CLNS implementations were either slow CORDIC-based or expensive 2D-table-based approaches. Instead, we reuse real LNS hardware for CLNS, with specialized hardware (including a novel \log \sin that overcomes singularity problems) that is smaller than the real-valued LNS ALU to which it is attached. All units were derived from the Floating-Point-Cores (FloPoCo) library. FPGA synthesis shows our CLNS ALU is smaller than prior fast CLNS units. We also compare the accuracy of prior and proposed CLNS implementations. The most accurate of the proposed methods increases the error in radix-two FFTs by less than half a bit, and a more economical FloPoCo-based implementation increases the error by only one bit.

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Index Terms:
Complex arithmetic, logarithmic number system, hardware function evaluation, FPGA, fast Fourier transform, VHDL.
Citation:
Mark G. Arnold, Sylvain Collange, "A Real/Complex Logarithmic Number System ALU," IEEE Transactions on Computers, vol. 60, no. 2, pp. 202-213, Feb. 2011, doi:10.1109/TC.2010.154
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