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Area-Efficient Multipliers Based on Multiple-Radix Representations
February 2011 (vol. 60 no. 2)
pp. 189-201
Vassil S. Dimitrov, University of Calgary, Calgary
Kimmo U. Järvinen, Aalto University, Aalto
Jithra Adikari, University of Calgary, Calgary
In this paper, we shall introduce several new algorithms for integer multiplication that are based on specific multiple-radix representation of one of the multiplicands. We provide extensive theoretical analysis and experimental results for multipliers based on the new representations on 0.18 {\rm \mu m} CMOS technology. They provide a clear picture about the advantages of the new method in 64-bit hardware implementations compared to array-based classical multiplier and radix-8-based multiplier. The proposed multipliers have better area and power consumption compared to reference multipliers.

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Index Terms:
Integer multiplication, multiple-radix representation, double-base number system.
Citation:
Vassil S. Dimitrov, Kimmo U. Järvinen, Jithra Adikari, "Area-Efficient Multipliers Based on Multiple-Radix Representations," IEEE Transactions on Computers, vol. 60, no. 2, pp. 189-201, Feb. 2011, doi:10.1109/TC.2010.200
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