Issue No.02 - February (2011 vol.60)
Fabrizio Lamberti , Politecnico di Torino, Torino
Nikos Andrikos , Politecnico di Torino, Torino
Elisardo Antelo , University of Santiago de Compostela, Santiago de Compostela
Paolo Montuschi , Politecnico di Torino, Torino
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.156
Two's complement multipliers are important for a wide range of applications. In this paper, we present a technique to reduce by one row the maximum height of the partial product array generated by a radix-4 Modified Booth Encoded multiplier, without any increase in the delay of the partial product generation stage. This reduction may allow for a faster compression of the partial product array and regular layouts. This technique is of particular interest in all multiplier designs, but especially in short bit-width two's complement multipliers for high-performance embedded cores. The proposed method is general and can be extended to higher radix encodings, as well as to any size square and m \times n rectangular multipliers. We evaluated the proposed approach by comparison with some other possible solutions; the results based on a rough theoretical analysis and on logic synthesis showed its efficiency in terms of both area and delay.
Multiplication, Modified Booth Encoding, partial product array.
Fabrizio Lamberti, Nikos Andrikos, Elisardo Antelo, Paolo Montuschi, "Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers", IEEE Transactions on Computers, vol.60, no. 2, pp. 148-156, February 2011, doi:10.1109/TC.2010.156