An Architecture for Fault-Tolerant Computation with Stochastic Logic

Weikang Qian; Kia Bazargan; David J. Lilja; Xin Li; Marc D. Riedel

doi:10.1109/TC.2010.202

Publication
2011
Issue No. 1 - January
Abstract - An Architecture for Fault-Tolerant Computation with Stochastic Logic

	This Article
	Subscribers, please Login Purchase article: $19 PDF HTML RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/EndNote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Weikang Qian Articles by Xin Li Articles by Marc D. Riedel Articles by Kia Bazargan Articles by David J. Lilja

An Architecture for Fault-Tolerant Computation with Stochastic Logic

January 2011 (vol. 60 no. 1)

pp. 93-105

	ASCII Text	x
	Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, David J. Lilja, "An Architecture for Fault-Tolerant Computation with Stochastic Logic," IEEE Transactions on Computers, vol. 60, no. 1, pp. 93-105, January, 2011.

	BibTex	x
	@article{ 10.1109/TC.2010.202, author = {Weikang Qian and Xin Li and Marc D. Riedel and Kia Bazargan and David J. Lilja}, title = {An Architecture for Fault-Tolerant Computation with Stochastic Logic}, journal ={IEEE Transactions on Computers}, volume = {60}, number = {1}, issn = {0018-9340}, year = {2011}, pages = {93-105}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2010.202}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - JOUR JO - IEEE Transactions on Computers TI - An Architecture for Fault-Tolerant Computation with Stochastic Logic IS - 1 SN - 0018-9340 SP93 EP105 EPD - 93-105 A1 - Weikang Qian, A1 - Xin Li, A1 - Marc D. Riedel, A1 - Kia Bazargan, A1 - David J. Lilja, PY - 2011 KW - Stochastic logic KW - reconfigurable hardware KW - fault-tolerant computation. VL - 60 JA - IEEE Transactions on Computers ER -

Weikang Qian, University of Minnesota, Minneapolis

Xin Li, University of Minnesota, Minneapolis

Marc D. Riedel, University of Minnesota, Minneapolis

Kia Bazargan, University of Minnesota, Minneapolis

David J. Lilja, University of Minnesota, Minneapolis

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.202

Mounting concerns over variability, defects, and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signals and so can cope with errors and uncertainty. Techniques for probabilistic analysis of circuits and systems are well established. We advocate a strategy for synthesis. In prior work, we described a methodology for synthesizing stochastic logic, that is to say logic that operates on probabilistic bit streams. In this paper, we apply the concept of stochastic logic to a reconfigurable architecture that implements processing operations on a datapath. We analyze cost as well as the sources of error: approximation, quantization, and random fluctuations. We study the effectiveness of the architecture on a collection of benchmarks for image processing. The stochastic architecture requires less area than conventional hardware implementations. Moreover, it is much more tolerant of soft errors (bit flips) than these deterministic implementations. This fault tolerance scales gracefully to very large numbers of errors.

[1] M. Mitzenmacher and E. Upfal, Probability and Computing: Randomized Algorithms and Probabilistic Analysis. Cambridge Univ. Press, 2005.
[2] C.H. Papadimitriou, Computational Complexity. Addison-Wesley, 1995.
[3] D.T. Gillespie, "A General Method for Numerically Simulating the Stochastic Time Evolution of Coupled Chemical Reactions," J. Computational Physics, vol. 22, no. 4, pp. 403-434, 1976.
[4] W. Qian and M.D. Riedel, "The Synthesis of Robust Polynomial Arithmetic with Stochastic Logic," Proc. 45th ACM/IEEE Design Automation Conf., pp. 648-653, 2008.
[5] W. Qian, J. Backes, and M.D. Riedel, "The Synthesis of Stochastic Circuits for Nanoscale Computation," Int'l J. Nanotechnology and Molecular Computation, vol. 1, no. 4, pp. 39-57, 2010.
[6] B. Gaines, "Stochastic Computing Systems," Advances in Information Systems Science, vol. 2, ch. 2, pp. 37-172, Plenum, 1969.
[7] S. Toral, J. Quero, and L. Franquelo, "Stochastic Pulse Coded Arithmetic," Proc. IEEE Int'l Symp. Circuits and Systems, vol. 1, pp. 599-602, 2000.
[8] B. Brown and H. Card, "Stochastic Neural Computation I: Computational Elements," IEEE Trans. Computers, vol. 50, no. 9, pp. 891-905, Sept. 2001.
[9] J. von Neumann, "Probabilistic Logics and the Synthesis of Reliable Organisms from Unreliable Components," Automata Studies, pp. 43-98, Princeton Univ. Press, 1956.
[10] E.F. Moore and C.E. Shannon, "Reliable Circuits Using Less Reliable Relays," J. Franklin Inst., vol. 262, pp. 191-208, 281-297, 1956.
[11] H. Chang and S. Sapatnekar, "Statistical Timing Analysis Under Spatial Correlations," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 9, pp. 1467-1482, Sept. 2005.
[12] D. Beece, J. Xiong, C. Visweswariah, V. Zolotov, and Y. Liu, "Transistor Sizing of Custom High-Performance Digital Circuits with Parametric Yield Considerations," Proc. 47th Design Automation Conf., pp. 781-786, 2010.
[13] K. Nepal, R. Bahar, J. Mundy, W. Patterson, and A. Zaslavsky, "Designing Logic Circuits for Probabilistic Computation in the Presence of Noise," Proc. 42nd Design Automation Conf., pp. 485-490, 2005.
[14] K. Palem, "Energy Aware Computing through Probabilistic Switching: A Study of Limits," IEEE Trans. Computers, vol. 54, no. 9, pp. 1123-1137, Sept. 2005.
[15] S. Narayanan, J. Sartori, R. Kumar, and D. Jones, "Scalable Stochastic Processors," Proc. Design, Automation and Test in Europe Conf. and Exhibition, pp. 335-338, 2010.
[16] J. Kim, N. Hardavellas, K. Mai, B. Falsafi, and J. Hoe, "Multi-Bit Error Tolerant Caches Using Two-dimensional Error Coding," Proc. 40th Ann. ACM/IEEE Int'l Symp. Microarchitecture, pp. 197-209, 2007.
[17] X. Li, W. Qian, M.D. Riedel, K. Bazargan, and D.J. Lilja, "A Reconfigurable Stochastic Architecture for Highly Reliable Computing," Proc. 19th ACM Great Lakes Symp. Very Large Scale Integration (VLSI), pp. 315-320, 2009.
[18] W. Qian, M.D. Riedel, K. Barzagan, and D. Lilja, "The Synthesis of Combinational Logic to Generate Probabilities," Proc. Int'l Conf. Computer-Aided Design, pp. 367-374, 2009.
[19] G. Lorentz, Bernstein Polynomials. Univ. of Toronto Press, 1953.
[20] D. Lee, R. Cheung, and J. Villasenor, "A Flexible Architecture for Precise Gamma Correction," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 4, pp. 474-478, Apr. 2007.
[21] J. Ortega, C. Janer, J. Quero, L. Franquelo, J. Pinilla, and J. Serrano, "Analog to Digital and Digital to Analog Conversion Based on Stochastic Logic," Proc. 21st IEEE Int'l Conf. Industrial Electronics, Control, and Instrumentation, pp. 995-999, 1995.
[22] H.P. Rosinger, Connecting Customized IP to the MicroBlaze Soft Processor Using the Fast Simplex Link Channel, Xilinx Inc., http://www.xilinx.com/support/documentation/ application_notesxapp529.pdf, 2004.
[23] Irotek, "EasyRGB," http://www.easyrgb.comindex.php?X= MATH, 2008.
[24] D. Phillips, Image Processing in C. R&D Publications, 1994.
[25] T. Urabe, "3D Examples," http://mathmuse.sci.ibaraki.ac.jp/geomparam1E.html , 2002.

Index Terms:

Stochastic logic, reconfigurable hardware, fault-tolerant computation.

Citation:

Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, David J. Lilja, "An Architecture for Fault-Tolerant Computation with Stochastic Logic," IEEE Transactions on Computers, vol. 60, no. 1, pp. 93-105, Jan. 2011, doi:10.1109/TC.2010.202

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.