Issue No.01 - January (2011 vol.60)
Zeshan Chishti , Intel Labs, Hillsboro
Alaa R. Alameldeen , Intel Labs, Hillsboro
Wei Wu , Intel Labs, Hillsboro
Shih-Lien Lu , Intel Labs, Hillsboro
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.207
The performance/energy trade-off is widely acknowledged as a primary design consideration for modern processors. A less discussed, though equally important, trade-off is the reliability/energy trade-off. Many design features that increase reliability (e.g., redundancy, error detection, and correction) have the side effect of consuming more energy. Many energy-saving features (e.g., voltage scaling) have the side effect of making systems less reliable. In this paper, we propose an adaptive cache design that enables the operating system to optimize for performance or energy efficiency without sacrificing reliability. Our proposed mechanism enables a cache with a wide operating range, where the cache can use a variable part of its data array to store error-correcting codes. A reliable, energy-efficient cache can use up to half of its data array to store error-correcting codes so that it can reliably operate at a low voltage to reduce energy. A reliable high-performance cache uses its whole data array, but operates at a higher voltage to improve reliability while sacrificing energy. We propose a hardware mechanism that allows the operating system to choose different points within that operating range based on the desired levels of performance, energy, and reliability.
Design, reliability, fault tolerance, dependable design.
Zeshan Chishti, Alaa R. Alameldeen, Wei Wu, Shih-Lien Lu, "Adaptive Cache Design to Enable Reliable Low-Voltage Operation", IEEE Transactions on Computers, vol.60, no. 1, pp. 50-63, January 2011, doi:10.1109/TC.2010.207