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A Counter Architecture for Online DVFS Profitability Estimation
November 2010 (vol. 59 no. 11)
pp. 1576-1583
Stijn Eyerman, Ghent University, Belgium
Lieven Eeckhout, Ghent University, Belgium
Dynamic voltage and frequency scaling (DVFS) is a well known and effective technique for reducing power consumption in modern microprocessors. An important concern though is to estimate its profitability in terms of performance and energy. Current DVFS profitability estimation approaches, however, lack accuracy or incur runtime performance and/or energy overhead. This paper proposes a counter architecture for online DVFS profitability estimation on superscalar out-of-order processors. The counter architecture teases apart the fraction of the execution time that is susceptible to clock frequency versus the fraction that is insusceptible to clock frequency. By doing so, the counter architecture can accurately estimate the performance and energy consumption at different V/f operating points from a single program execution. The DVFS counter architecture estimates performance, energy consumption, and energy-delay-squared-product ({\rm ED}^2{\rm P}) within 0.2, 0.5, and 0.8 percent on average, respectively, over a 4{\times} frequency range. Further, the counter architecture incurs a small hardware cost and is an enabler for online DVFS scheduling both at the intracore as well as at the intercore level in a multicore processor.

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Index Terms:
Computer systems organization, performance of systems, modeling techniques, modeling of computer architecture, power management.
Citation:
Stijn Eyerman, Lieven Eeckhout, "A Counter Architecture for Online DVFS Profitability Estimation," IEEE Transactions on Computers, vol. 59, no. 11, pp. 1576-1583, Nov. 2010, doi:10.1109/TC.2010.65
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