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Issue No.11 - November (2010 vol.59)
pp: 1455-1465
Martin Omaña , University of Bologna, Bologna
Daniele Rossi , University of Bologna, Bologna
Cecilia Metra , University of Bologna, Bologna
ABSTRACT
First, a new high-performance robust latch (referred to as HiPeR latch) is presented that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good trade-offs in terms of performance, robustness, and cost, our proposed latches are particularly suitable to be adopted on critical paths.
INDEX TERMS
Transient faults, soft errors, static latch, hardened latch, robust design.
CITATION
Martin Omaña, Daniele Rossi, Cecilia Metra, "High-Performance Robust Latches", IEEE Transactions on Computers, vol.59, no. 11, pp. 1455-1465, November 2010, doi:10.1109/TC.2010.24
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