This Article 
 Bibliographic References 
 Add to: 
Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors
October 2010 (vol. 59 no. 10)
pp. 1402-1418
Alex Bobrek, ExxonMobile Upstream Research Company, Houston
JoAnn M. Paul, Virginia Tech, Blacksburg
Donald E. Thomas, Carnegie Mellon University, Pittsburgh
Single-chip systems, featuring multiple heterogeneous processors and a variety of communication and memory architectures, have emerged to satisfy the demand for networking, handheld computing, and other custom devices. When simulated at cycle-accurate level, these system models are slow to build and execute, severely limiting the number of design iterations that can be considered. A key challenge in raising the simulation level above the clock cycle is an effective method for estimating contention for shared resources such as memories and busses. This paper introduces a new level of design called the Stochastic Contention Level (SCL). Instead of considering shared resource accesses at the clock cycle granularity, SCL simulations operate on blocks that are thousands to millions of clock cycles long, stochastically capturing contention for shared resources via sampled access attributes, while still retaining an event-based simulation framework. The SCL approach results in speedups of 40{\times} over cycle-accurate simulation, with average simulation errors of less than one percent with 95 percent confidence intervals of about \pm 3 {\rm percent}, providing a unique combination of simulation capabilities, performance, and accuracy. This significant increase in simulation performance enables the system designers to explore more of the design space than possible with traditional simulation approaches.

[1] V.S. Adve and M.K. Vernon, "Parallel Program Performance Prediction Using Deterministic Task Graph Analysis," ACM Trans. Computer Systems, vol. 22, no. 1, pp. 94-136, 2004.
[2] J.R. Bammi, W. Kruijtzer, L. Lavagno, E. Harcourt, and M.T. Lazarescu, "Software Performance Estimation Strategies in a System-Level Design Tool," Proc. Int'l Workshop Hardware/Software Codesign (CODES '00), pp. 82-86, 2000.
[3] M.V. Biesbrouck, T. Sherwood, and B. Calder, "A Co-Phase Matrix to Guide Simultaneous Multithreading Simulation," Proc. IEEE Int'l Symp. Performance Analysis of Systems and Software (ISPASS '04), pp. 45-56, 2004.
[4] A. Bobrek, "A Statistical Approach to Contention Modeling for High-Level Heterogeneous Multiprocessor Simulation," PhD thesis, Carnegie Mellon Univ., Technical Report No. CSSI-07-03, Nov. 2007.
[5] A. Bobrek, J.M. Paul, and D.E. Thomas, "Event-Based Re-Training of Statistical Contention Models for Heterogeneous Multiprocessors," Proc. IEEE/ACM Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS '07), pp. 69-74, 2007.
[6] A. Bobrek, J.M. Paul, and D.E. Thomas, "Shared Resource Access Attributes for High-Level Contention Models," Proc. Ann. Design Automation Conf. (DAC '07), pp. 720-725, 2007.
[7] A. Bobrek, J.J. Pieper, J.E. Nelson, J.M. Paul, and D.E. Thomas, "Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach," Proc. Conf. Design, Automation and Test in Europe (DATE '04), pp. 1144-1149, 2004.
[8] R. Covington, J. Jump, and J. Sinclair, "Cross-Profiling As an Efficient Technique in Simulating Parallel Computer Systems," Proc. Computer Software and Applications Conf., pp. 75-80, 1989.
[9] L. Eeckhout, S. Nussbaum, J.E. Smith, and K. De Bosschere, "Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox," IEEE Micro, vol. 23, no. 5, pp. 26-38, Sept./Oct. 2003.
[10] M.I. Frank, A. Agarwal, and M.K. Vernon, "LoPC: Modeling Contention in Parallel Algorithms," Proc. ACM SIGPLAN Symp. Principles and Practice of Parallel Programming (PPOPP '97), pp. 276-287, 1997.
[11] The R Project for Statistical Computing, http:/www.r-project. org/, 2010.
[12] P.J. Joseph, K. Vaswani, and M.J. Thazhuthaveetil, "Construction and Use of Linear Regression Models for Processor Performance Analysis," Proc. Int'l Symp. High Performance Computer Architecture (HPCA '06), 2006.
[13] A. Joshi, J.J. Yi, R.H. Bell, L. Eeckhout, L. John, and D.J. Lilja, "Evaluating the Efficacy of Statistical Simulation for Design Space Exploration," Proc. IEEE Int'l Symp. Performance Analysis of Systems and Software (ISPASS '06), pp. 70-79, 2006.
[14] M. Lajolo, M. Lazarescu, and A. Sangiovanni-Vincentelli, "A Compilation-Based Software Estimation Scheme for Hardware/Software Co-Simulation," Proc. Int'l Workshop Hardware/Software Codesign (CODES '99), pp 85-89, 1999.
[15] B.C. Lee and D.M. Brooks, "Accurate and Efficient Regression Modeling for Microarchitectural Performance and Power Prediction," Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '06), J.P. Shen and M. Martonosi, eds., pp. 185-194, 2006.
[16] J. Paul and D. Thomas, "A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems," Proc. Conf. Design, Automation and Test in Europe (DATE '02), p. 522, 2002.
[17] J.M. Paul, D.E. Thomas, and A. Bobrek, "Scenario-Oriented Design for Single-Chip Heterogeneous Multiprocessors," IEEE Trans. Very Large Scale Integration Systems, vol. 14, no. 8, pp. 868-880, Aug. 2006.
[18] S.M. Pieper, J.M. Paul, and M.J. Schulte, "A New Era of Performance Evaluation," Computer, vol. 40, no. 9, pp. 23-30, Sept. 2007.
[19] T. Sherwood, E. Perelman, G. Hamerly, S. Sair, and B. Calder, "Discovering and Exploiting Program Phases," IEEE Micro, vol. 23, no. 5, pp. 26-38, Nov./Dec. 2003.
[20] D.J. Sorin, V.S. Pai, S.V. Adve, M.K. Vernon, and D.A. Wood, "Analytic Evaluation of Shared-Memory Systems with ILP Processors," Proc. Int'l Symp. Computer Architecture (ISCA '98), pp. 380-391, 1998.
[21] T.F. Wenisch, R.E. Wunderlich, M. Ferdman, A. Ailamaki, B. Falsafi, and J.C. Hoe, "SimFlex: Statistical Sampling of Computer System Simulation," IEEE Micro, vol. 26, no. 4, pp. 18-31, July/Aug. 2006.

Index Terms:
Performance modeling, simulation, contention modeling, stochastic contention level, statistical regression models, heterogeneous multiprocessors.
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas, "Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors," IEEE Transactions on Computers, vol. 59, no. 10, pp. 1402-1418, Oct. 2010, doi:10.1109/TC.2010.19
Usage of this product signifies your acceptance of the Terms of Use.