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Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
October 2010 (vol. 59 no. 10)
pp. 1363-1377
ASCII Text
x 
 
Holger Lange, Andreas Koch, "Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization," IEEE Transactions on Computers, vol. 59, no. 10, pp. 1363-1377, October, 2010.
 
 
BibTex
x
 
@article{ 10.1109/TC.2009.180,
author = {Holger Lange and Andreas Koch},
title = {Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization},
journal ={IEEE Transactions on Computers},
volume = {59},
number = {10},
issn = {0018-9340},
year = {2010},
pages = {1363-1377},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2009.180},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
IS - 10
SN - 0018-9340
SP1363
EP1377
EPD - 1363-1377
A1 - Holger Lange,
A1 - Andreas Koch,
PY - 2010
KW - Reconfigurable computing
KW - FPGA
KW - hardware accelerator
KW - memory system
KW - operating system integration
KW - virtual memory.
VL - 59
JA - IEEE Transactions on Computers
ER -
 
Holger Lange, Technische Universität Darmstadt, Darmstadt
Andreas Koch, Technische Universität Darmstadt, Darmstadt
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator (HA), the latter having full master-mode access to memory. We then describe how the resulting requirements can actually be realized efficiently in a custom computer by hardware architecture and system software measures. One of these is a low-latency HA-to-GPP signaling scheme with latency up to 23{\times} times shorter than conventional approaches. Another one is a high-bandwidth shared memory interface that does not interfere with time-critical operating system functions executing on the GPP, and still makes 89 percent of the physical memory bandwidth available to the HA. Finally, we show two schemes with different flexibility/performance trade-offs for running the HA in protected virtual memory scenarios. All of the techniques and their interactions are evaluated at the system level using the full-scale virtual memory variant of the Linux operating system on actual hardware.

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Index Terms:
Reconfigurable computing, FPGA, hardware accelerator, memory system, operating system integration, virtual memory.
Citation:
Holger Lange, Andreas Koch, "Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization," IEEE Transactions on Computers, vol. 59, no. 10, pp. 1363-1377, Oct. 2010, doi:10.1109/TC.2009.180
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