
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Sylvain Guilley, Laurent Sauvage, Florent Flament, VinhNga Vong, Philippe Hoogvorst, Renaud Pacalet, "Evaluation of Power Constant DualRail Logics Countermeasures against DPA with Design Time Security Metrics," IEEE Transactions on Computers, vol. 59, no. 9, pp. 12501263, September, 2010.  
BibTex  x  
@article{ 10.1109/TC.2010.104, author = {Sylvain Guilley and Laurent Sauvage and Florent Flament and VinhNga Vong and Philippe Hoogvorst and Renaud Pacalet}, title = {Evaluation of Power Constant DualRail Logics Countermeasures against DPA with Design Time Security Metrics}, journal ={IEEE Transactions on Computers}, volume = {59}, number = {9}, issn = {00189340}, year = {2010}, pages = {12501263}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2010.104}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Evaluation of Power Constant DualRail Logics Countermeasures against DPA with Design Time Security Metrics IS  9 SN  00189340 SP1250 EP1263 EPD  12501263 A1  Sylvain Guilley, A1  Laurent Sauvage, A1  Florent Flament, A1  VinhNga Vong, A1  Philippe Hoogvorst, A1  Renaud Pacalet, PY  2010 KW  cryptography KW  implementationlevel security KW  sidechannel analysis KW  leakage metrics KW  AES SubBytes KW  dualrail with precharge logics (DPL) KW  attacks on DPL KW  backendlevel protections. VL  59 JA  IEEE Transactions on Computers ER   
[1] P. Kocher, J. Jaffe, and B. Jun, "Differential Power Analysis: LeakingSecrets," Proc. Ann. Int'l Conf. Cryptology (CRYPTO '99), pp. 388397, http://www.cryptography.com/resources/ whitepapers DPA.pdf, Aug. 1999.
[2] É. Brier, C. Clavier, and F. Olivier, "Correlation Power Analysis with a Leakage Model," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES '04), pp. 1629, Aug. 2004.
[3] J.L. Danger, S. Guilley, S. Bhasin, and M. Nassar, "Overview of Dual Rail with Precharge Logic Styles to Thwart ImplementationLevel Attacks on Hardware Cryptoprocessors,—New Attacks and Improved CounterMeasures," Proc. Workshop Secure Control Systems (SCS), Nov. 2009.
[4] K. Tiri and I. Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation," Proc. Conf. Design, Automation, and Test in Europe (DATE '04), pp. 246251, Feb. 2004.
[5] S. Guilley, F. Flament, R. Pacalet, P. Hoogvorst, and Y. Mathieu, "Security Evaluation of a Secured QuasiDelay Insensitive Library," Proc. Conf. Design of Circuits and Integrated Systems (DCIS '08), pp. 17, http://hal.archivesouvertes.fr/hal00283405 en/, Nov. 2008.
[6] T. Popp and S. Mangard, "Masked DualRail PreCharge Logic: DPAResistance without Routing Constraints," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES '05), pp. 172186, Sept. 2005.
[7] P. Schaumont and K. Tiri, "Masking and Dual Rail Logic Don't Add Up," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES), pp. 95106, 2007.
[8] NIST/ITL/CSD, "FIPS PUB 197: Advanced Encryption Standard (AES)," http://csrc.nist.gov/publications/fips/fips197 fips197. pdf, Nov. 2001.
[9] S. Guilley, P. Hoogvorst, Y. Mathieu, R. Pacalet, and J. Provost, "CMOS Structures Suitable for Secured Hardware," Proc. Conf. Design, Automation, and Test in Europe (DATE '04), pp. 14141415, Feb. 2004.
[10] S. Moore, R. Anderson, R. Mullins, G. Taylor, and J.J.A. Fournier, "Balanced SelfChecking Asynchronous Logic for Smart Card Applications," J. Microprocessors and Microsystems, vol. 27, pp. 421430, Oct. 2003.
[11] V. Rijmen, "Efficient Implementation of the Rijndael SBox," Informal Communication, 2000.
[12] A. Rudra, P.K. Dubey, C.S. Jutla, V. Kumar, J.R. Rao, and P. Rohatgi, "Efficient Rijndael Encryption Implementation with Composite Field Arithmetic," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES), pp. 171184, May 2001.
[13] J. Wolkerstorfer, E. Oswald, and M. Lamberger, "An ASIC Implementation of the AES SBoxes," Proc. The Cryptographer's Track at the RSA Conf. Topics in Cryptology (CTRSA), pp. 6778, 2002.
[14] G. Bertoni, M. Macchetti, L. Negri, and P. Fragneto, "PowerEfficient ASIC Synthesis of Cryptographic SBoxes," Proc. 14th ACM Great Lakes Symp. VLSI (GLSVLSI '04), pp. 277281, Apr. 2004.
[15] M. Giaconia, M. Macchetti, F. Regazzoni, and K. Schramm, "Area and Power Efficient Synthesis of DPAResistant Cryptographic SBoxes," Proc. Int'l Conf. VLSI Design, pp. 731737, Jan. 2007.
[16] S. Tillich, M. Feldhofer, and J. Großschädl, "Area, Delay, and Power Characteristics of StandardCell Implementations of the AES SBox," Proc. Int'l Symp. Systems, Architectures, Modeling, and Simulation (SAMOS), pp. 457466, July 2006.
[17] S. Tillich, M. Feldhofer, T. Popp, and J. Großschädl, "Area, Delay, and Power Characteristics of StandardCell Implementations of the AES SBox," J. Signal Processing Systems, vol. 50, no. 2, pp. 251261, 2008.
[18] D. Suzuki and M. Saeki, "Security Evaluation of DPA Countermeasures Using DualRail Precharge Logic Style," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES '06), pp. 255269, 2006.
[19] M. Shams, J. Ebergen, and M. Elmasry, "Modeling and Comparing CMOS Implementations of the CElement," IEEE Trans. Very Large Scale Integration Systems, vol. 6, no. 4, pp. 563567, Dec. 1998.
[20] S. Guilley, P. Hoogvorst, Y. Mathieu, and R. Pacalet, "The 'Backend Duplication' Method," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES '05), pp. 383397, Aug. 2005.
[21] S. Guilley, F. Flament, R. Pacalet, P. Hoogvorst, and Y. Mathieu, "Secured CAD BackEnd Flow for PowerAnalysis Resistant Cryptoprocessors," IEEE Design and Test of Computers, special issue on Design and Test of ICs for Secure Embedded Computing, vol. 24, no. 6, pp. 546555, Nov./Dec. 2007.
[22] K. Gandolfi, C. Mourtel, and F. Olivier, "Electromagnetic Analysis: Concrete Results," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES '01), pp. 251261, May 2001.
[23] S. Guilley, S. Chaudhuri, L. Sauvage, P. Hoogvorst, R. Pacalet, and G.M. Bertoni, "Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks," IEEE Trans. Computers, vol. 57, no. 11, pp. 14821497, Nov. 2008.
[24] S. Mangard, N. Pramstaller, and E. Oswald, "Successfully Attacking Masked AES Hardware Implementations," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES '05), pp. 157171, Sept. 2005.
[25] S. Guilley, P. Hoogvorst, and R. Pacalet, "Differential Power Analysis Model and Some Results," Proc. Int'l Conf. Smart Card Research and Advanced Application (CARDIS '04), pp. 127142, Aug. 2004.
[26] E. Prouff, "DPA Attacks and SBoxes," Proc. Int'l Symp. Foundations of Software Eng. (FSE '05), pp. 424441, Feb. 2005.
[27] C. Carlet, "On Highly Nonlinear SBoxes and Their Inability to Thwart DPA Attacks," Proc. Int'l Conf. Cryptology in India (INDOCRYPT '05), pp. 4962, Dec. 2005.
[28] S. Guilley, P. Hoogvorst, R. Pacalet, and J. Schmidt, "Improving SideChannel Attacks by Exploiting Substitution Boxes Properties," Proc. Int'l Workshop Boolean Functions: Cryptography and Applications (BFCA), pp. 125, http://www.liafa.jussieu.fr/bfca/booksBFCA07.pdf , May 2007.
[29] Institute of Electrical and Electronics Engineers, "IEEE Standard VHDL (Very High Speed Integrated Circuits Description Language) Reference Manual," pp. 1300, http:/www.ieee.org/, 2002.
[30] C. Archambeau, É. Peeters, F.X. Standaert, and J.J. Quisquater, "Template Attacks in Principal Subspaces," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES), pp. 114, 2006.
[31] F. Macé, F.X. Standaert, and J.J. Quisquater, "Information Theoretic Evaluation of SideChannel Resistant Logic Styles," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES), pp. 427442, Sept. 2007.
[32] F. Regazzoni, A. Cevrero, F.X. Standaert, S. Badel, T. Kluter, P. Brisk, Y. Leblebici, and P. Ienne, "A Design Flow and Evaluation Framework for DPAResistant Instruction Set Extensions," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES), pp. 205219, Sept. 2009.
[33] K. Tiri and I. Verbauwhede, "Place and Route for Secure Standard Cell Design," Proc. IFIP World Congress (WCC)/Int'l Conf. Smart Card Research and Advanced Application (CARDIS), pp. 143158, Aug. 2004.
[34] É. Peeters, "Towards Security Limits of Embedded Hardware Devices: From Practice to Theory," PhD dissertation, Ucl Crypto Group, Univ. catholique de Louvain, Nov. 2006.
[35] N. Hanley, R. McEvoy, M. Tunstall, C. Whelan, C. Murphy, and W.P. Marnane, "Correlation Power Analysis of Large Word Sizes," Proc. Irish Signals and System Conf. (ISSC), pp. 145150, Sept. 2007.
[36] S. Guilley, S. Chaudhuri, L. Sauvage, T. Graba, J.L. Danger, P. Hoogvorst, V.N. Vong, and M. Nassar, "PlaceandRoute Impact on the Security of DPL Designs in FPGAs," Proc. IEEE Int'l Workshop HardwareOriented Security and Trust (HOST), pp. 2935, June 2008.
[37] H. Li, A. Markettos, and S. Moore, "A Security Evaluation Methodology for Smart Cards against Electromagnetic Analysis," Proc. 39th Ann. Int'l Carnahan Conf. Security Technology (CCST '05), pp. 208211, Oct. 2005.
[38] G.D. Natale, M.L. Flottes, and B. Rouzeyre, "An Integrated Validation Environment for Differential Power Analysis," Proc. IEEE Int'l Symp. Electronic Design, Test and Applications (DELTA), pp. 527532, Jan. 2008.
[39] A. Satoh, "SideChannel Attack Standard Evaluation Board, SASEBO," project of the AIST—Research Center for Information Security (RCIS), http://www.rcis.aist.go.jp/specialSASEBO /, 2010.
[40] EveSoC Software "A SideChannel Eavesdropping SystemonChip," http://sourceforge.net/projectsevesoc/, 2010.