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Issue No.08 - August (2010 vol.59)

pp: 1145-1151

Ming-Der Shieh , National Cheng Kung University, Tainan

Wen-Ching Lin , National Cheng Kung University, Tainan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.72

ABSTRACT

Modular multiplication is a crucial operation in public key cryptosystems like RSA and elliptic curve cryptography (ECC). This paper presents a new word-based Montgomery modular multiplication algorithm which can be used to achieve a low-latency scalable architecture for efficient hardware implementations. We show how to relax the data dependency in conventional word-based algorithms so that a latency of exactly one cycle can be obtained regardless of the chosen word size w (w > 1). With the presented operand reduction scheme, the proposed scalable architecture can operate at high speeds and suitable data paths can be chosen for specific applications. Complexity analysis shows that the proposed architecture has the lowest latency and area complexity compared to related scalable architectures. Experimental results demonstrate that our design has area, speed, and flexibility advantages over related schemes.

INDEX TERMS

Algorithms implemented in hardware, computations in finite fields, computer arithmetic, high-speed arithmetic, VLSI.

CITATION

Ming-Der Shieh, Wen-Ching Lin, "Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures",

*IEEE Transactions on Computers*, vol.59, no. 8, pp. 1145-1151, August 2010, doi:10.1109/TC.2010.72REFERENCES