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A Reduced Complexity Wallace Multiplier Reduction
August 2010 (vol. 59 no. 8)
pp. 1134-1137
ASCII Text
x 
 
Ron S. Waters, Earl E. Swartzlander, "A Reduced Complexity Wallace Multiplier Reduction," IEEE Transactions on Computers, vol. 59, no. 8, pp. 1134-1137, August, 2010.
 
 
BibTex
x
 
@article{ 10.1109/TC.2010.103,
author = {Ron S. Waters and Earl E. Swartzlander},
title = {A Reduced Complexity Wallace Multiplier Reduction},
journal ={IEEE Transactions on Computers},
volume = {59},
number = {8},
issn = {0018-9340},
year = {2010},
pages = {1134-1137},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2010.103},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - A Reduced Complexity Wallace Multiplier Reduction
IS - 8
SN - 0018-9340
SP1134
EP1137
EPD - 1134-1137
A1 - Ron S. Waters,
A1 - Earl E. Swartzlander,
PY - 2010
KW - High-speed multiplier
KW - Wallace multiplier
KW - Dadda multiplier.
VL - 59
JA - IEEE Transactions on Computers
ER -
 
Ron S. Waters, University of Texas at Austin, Austin, TX
Earl E. Swartzlander, University of Texas at Austin, Austin, TX
Wallace high-speed multipliers use full adders and half adders in their reduction phase. Half adders do not reduce the number of partial product bits. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity. A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction. The modified reduction method greatly reduces the number of half adders; producing implementations with 80 percent fewer half adders than standard Wallace multipliers, with a very slight increase in the number of full adders.

[1] C.S. Wallace, "A Suggestion for a Fast Multiplier," IEEE Trans. Electronic Computers, vol. 13, no. 1, pp. 14-17, Feb. 1964.
[2] E. Bloch, "The Engineering Design of the Stretch Computer," Proc. Eastern Joint IRE-AIEE-ACM Computer Conf., no. 16, pp. 48-58, 1959.
[3] L. Dadda, "Some Schemes for Parallel Multipliers," Alta Frequenza, vol. 34, pp. 349-356, 1965.
[4] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford Univ. Press, p. 179, 2000.
[5] K.C. Bickerstaff, M.J. Schulte, and E.E. SwartzlanderJr., "Parallel Reduced Area Multipliers," J. VLSI Signal Processing Systems, vol. 9, no. 3, pp. 181-191, Apr. 1995.
[6] W.J. Townsend, E.E. SwartzlanderJr., and J.A. Abraham, "A Comparison of Dadda and Wallace Multiplier Delays," Proc. SPIE, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, pp. 552-560, 2003.
[7] R.S. Waters, MATLAB based Wallace and Modified Wallace Multiplier Generator Programs, http:\\ronwaters.com\, 2007.

Index Terms:
High-speed multiplier, Wallace multiplier, Dadda multiplier.
Citation:
Ron S. Waters, Earl E. Swartzlander, "A Reduced Complexity Wallace Multiplier Reduction," IEEE Transactions on Computers, vol. 59, no. 8, pp. 1134-1137, Aug. 2010, doi:10.1109/TC.2010.103
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