Issue No.08 - August (2010 vol.59)
Ron S. Waters , University of Texas at Austin, Austin, TX
Earl E. Swartzlander , University of Texas at Austin, Austin, TX
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.103
Wallace high-speed multipliers use full adders and half adders in their reduction phase. Half adders do not reduce the number of partial product bits. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity. A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction. The modified reduction method greatly reduces the number of half adders; producing implementations with 80 percent fewer half adders than standard Wallace multipliers, with a very slight increase in the number of full adders.
High-speed multiplier, Wallace multiplier, Dadda multiplier.
Ron S. Waters, Earl E. Swartzlander, "A Reduced Complexity Wallace Multiplier Reduction", IEEE Transactions on Computers, vol.59, no. 8, pp. 1134-1137, August 2010, doi:10.1109/TC.2010.103