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Heuristics for Flexible CMP Synthesis
August 2010 (vol. 59 no. 8)
pp. 1091-1104
ASCII Text
x 
 
Harold Ishebabi, Christophe Bobda, "Heuristics for Flexible CMP Synthesis," IEEE Transactions on Computers, vol. 59, no. 8, pp. 1091-1104, August, 2010.
 
 
BibTex
x
 
@article{ 10.1109/TC.2010.77,
author = {Harold Ishebabi and Christophe Bobda},
title = {Heuristics for Flexible CMP Synthesis},
journal ={IEEE Transactions on Computers},
volume = {59},
number = {8},
issn = {0018-9340},
year = {2010},
pages = {1091-1104},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2010.77},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Heuristics for Flexible CMP Synthesis
IS - 8
SN - 0018-9340
SP1091
EP1104
EPD - 1091-1104
A1 - Harold Ishebabi,
A1 - Christophe Bobda,
PY - 2010
KW - Reconfigurable computing
KW - chip multiprocessor systems
KW - parallel programs.
VL - 59
JA - IEEE Transactions on Computers
ER -
 
Harold Ishebabi, University of Potsdam, Potsdam
Christophe Bobda, University of Potsdam, Potsdam
Flexible Chip Multiprocessor (CMP) systems are implemented on field programmable devices to exploit both task-level parallelism and architecture customization for parallel programs. The idea is to simultaneously allocate processor resources, map and schedule tasks to them, and to allocate one or several intertask communication resources such that the throughput or execution time is optimized. The design space of such systems is huge, requiring means to automatically optimize design parameters so as to facilitate wide and disciplined explorations. The complexity resulting from corresponding system modeling necessitates the use of optimization heuristics to cope with excessively long runtime for large problem instances. This paper provides a formal proof for the existence of optimum linear time synthesis algorithms for one of two classes of problem instances, and proceeds to present three greedy-like heuristics which exploit the structure of the synthesis problem. A comparison of results for real-time and non-real-time parallel programs is given against integer linear programming, where a synthesis strategy is proposed to achieve good results.

[1] C. Bobda, T. Haller, F. Muehlbauer, D. Rech, and S. Jung, "Design of Adaptive Multiprocessor on Chip Systems," Proc. 20th Ann. Conf. Symp. Integrated Circuits and Systems Design (SBCCI '07), pp. 177-183, 2007.
[2] W.-T. Zhang, L.-F. Geng, D.-L. Zhang, G.-M. Du, M.-L. Gao, W. Zhang, and Y.-H.T. Ning Hou, "Design of Heterogeneous MPSoC on FPGA," Proc. IEEE Seventh Int'l Conf. ASIC (ASICON '07), pp. 102-105, 2007.
[3] M. Saldana, D. Nunes, E. Ramalho, and P. Chow, "Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI," Proc. IEEE Int'l Conf. Reconfigurable Computing and FPGA's, pp. 1-10, 2006.
[4] N. Njoroge, J. Casper, S. Wee, Y. Teslyar, D. Ge, C. Kozyrakis, and K. Olukotun, "Atlas: A Chip-Multiprocessor with Transactional Memory Support," Proc. Conf. Design, Automation and Test in Europe (DATE '07), pp. 3-8, 2007.
[5] C. Bobda, Introduction to Reconfigurable Computing. Springer, 2007.
[6] H. Ishebabi and C. Bobda, "Automated Architecture Synthesis for Adaptive Multiprocessors on Chip Systems," J. Microprocessors and Microsystems, Feb. 2009.
[7] M. Gries and K. Keutzer, Building ASIPs: The Mescal Methodology. Springer-Verlag New York, 2005.
[8] A. Chattopadhyay, X. Chen, H. Ishebabi, R. Leupers, G. Ascheid, and H. Meyr, "High-Level Modelling and Exploration of Coarse-Grained Re-Configurable Architectures," Proc. Conf. Design, Automation and Test in Europe (DATE '08), pp. 1334-1339, 2008.
[9] A. Wieferink, T. Kogel, R. Leupers, G. Ascheid, H. Meyr, G. Braun, and A. Nohl, "A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms," Proc. Conf. Design, Automation and Test in Europe (DATE '04), p. 21256, 2004.
[10] F. Fummi, S. Martini, G. Perbellini, and M. Poncino, "Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC," Proc. Conf. Design, Automation and Test in Europe (DATE '04), p. 10564, 2004.
[11] K. Goossens, J. Dielissen, and A. Radulescu, "Aethereal Network on Chip: Concepts, Architectures, and Implementations," IEEE Design & Test of Computers, vol. 22, no. 5, pp. 414-421, Sept.-Oct. 2005.
[12] S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, P. Iyer, A. Singh, T. Jacob, S. Jain, S. Venkataraman, Y. Hoskote, and N. Borkar, "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC '07), pp. 98-589, Feb. 2007.
[13] E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "QNoC: QoS Architecture and Design Process for Network on Chip," J. Systems Architecture, vol. 50, nos. 2-3, pp. 105-128, 2004.
[14] A. Hansson, K. Goossens, and A. Rădulescu, "A Unified Approach to Constrained Mapping Routing on Network-on-Chip Architectures," Proc. Third IEEE/ACM/IFIP Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS '05), pp. 75-80, 2005.
[15] P.P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance Evaluation and Design Trade Offs for Network-on-Chip Interconnect Architectures," IEEE Trans. Computers, vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
[16] M. Moadeli, A. Shahrabi, and W. Vanderbauwhede, "Analytical Modelling of Communication in the Rectangular Mesh Noc," Proc. 13th Int'l Conf. Parallel and Distributed Systems, vol. 2, pp. 1-8, Dec. 2007.
[17] P. Wolkotte, P. Holzenspies, and G. Smit, "Fast, Accurate and Detailed NoC Simulations" Proc. First ACM/IEEE Int'l Symp. Networks-on-Chip (NOCS '07), pp. 323-332, May 2007.
[18] D. Quinn, B. Lavigueur, G. Bois, and M. Aboulhamid, "A System Level Exploration Platform Methodology for Network Applications Based on Configurable Processors," Proc. Conf. Design, Automation and Test in Europe (DATE '04), p. 10364, 2004.
[19] S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration," Proc. 41st Ann. ACM/IEEE Design Automation Conf. (DAC), pp. 113-118, 2004.
[20] R.B. Mouhoub and O. Hammami, "MOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution," EURASIP J. Embedded Systems, vol. 2006, no. 1, p. 12, 2006.
[21] Y. Jin, N. Satish, K. Ravindran, and K. Keutzer, "An Automated Exploration Framework for FPGA-Based Soft Multiprocessor Systems," Proc. Third IEEE/ACM/IFIP Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS '05), pp. 273-278, 2005.
[22] G. Beltrame, D. Bruschi, D. Sciuto, and C. Silvano, "Decision-Theoretic Exploration of Multiprocessor Platforms," Proc. Fourth IEEE/ACM/IFIP Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS '06), pp. 205-210, 2006.
[23] C. Lee and S. Ha, "Hardware-Software Cosynthesis of Multitask MPSoCs with Real-Time Constraints," Proc. IEEE Sixth Int'l Conf. ASIC, vol. 2, pp. 919-924, 2005.
[24] C. Chang, J. Wawrzynek, and R.W. Brodersen, "BEE2: A High-End Reconfigurable Computing System," IEEE Design & Test of Computers, vol. 22, no. 2, pp. 114-125, Mar.-Apr. 2005.
[25] B.K. Dwivedi, A. Kumar, and M. Balakrishnan, "Automatic Synthesis of System on Chip Multiprocessor Architectures for Process Networks," Proc. Second IEEE/ACM/IFIP Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS '04), pp. 60-65, 2004.
[26] B. Meyer and D. Thomas, "Rethinking Automated Synthesis of MPSoC Architectures," Proc. IEEE Int'l Parallel and Distributed Processing Symp. (IPDPS '07), pp. 1-6, Mar. 2007.
[27] S. Kang and R. Kumar, "Magellan: A Search and Machine Learning-Based Framework for Fast Multi-Core Design Space Exploration and Optimization," Proc. Conf. Design, Automation and Test in Europe (DATE '08), pp. 1432-1437, Mar. 2008.
[28] D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini, and G.D. Micheli, "NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip," IEEE Trans. Parallel and Distributed Systems, vol. 16, no. 2, pp. 113-129, Feb. 2005.
[29] P. Pop, "Analysis and Synthesis of Communication Intensive Heterogeneous Real-Time Systems," PhD dissertation, Linkoping Univ., 2003.
[30] D.L. Rhodes and W. Wolf, "Co-Synthesis of Heterogeneous Multiprocessor Systems Using Arbitrated Communication," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '99), pp. 339-342, 1999.
[31] C. Erbas, S. Cerav-Erbas, and A. Pimentel, "Multiobjective Optimization and Evolutionary Algorithms for the Application Mapping Problem in Multiprocessor System-on-Chip Design," IEEE Trans. Evolutionary Computation, vol. 10, no. 3 pp. 358-374, June 2006.
[32] M. Bao, A. Andrei, P. Eles, and Z. Peng, "Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling," Proc. 11th IEEE Workshop Design and Diagnostics of Electronic Circuits and Systems (DDECS '08), pp. 1-6, Apr. 2008.
[33] M. Ruggiero, A. Guerri, D. Bertozzi, F. Poletti, and M. Milano, "Communication-Aware Allocation Scheduling Framework for Stream-Oriented Multi-Processor Systems-on-Chip," Proc. Conf. Design, Automation and Test in Europe (DATE '06), pp. 3-8, 2006.
[34] S. Carta, F. Mereu, A. Acquaviva, and G. Micheli, "MiGra: A Task Migration Algorithm for Reducing Temperature Gradient in Multiprocessor Systems on Chip," Proc. Int'l Symp. System-on-Chip, pp. 1-6, Nov. 2007.
[35] P.K. Holzenspies, J.L. Hurink, J. Kuper, and G.J. Smit, "Run-Time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC)," Proc. Conf. Design, Automation and Test in Europe (DATE '08), pp. 212-217, Mar. 2008.
[36] H. Ishebabi, P. Mahr, and C. Bobda, "Makespan Minimization in Automatic Synthesis of Multiprocessor Systems from Parallel Programs," Proc. IEEE Int'l Conf. Field-Programmable Technology, Dec. 2008.
[37] T.T. Cormen, C.E. Leiserson, and R.L. Rivest, Introduction to Algorithms. MIT Press, 1990.
[38] H. Ishebabi, P. Mahr, and C. Bobda, "Automatic Synthesis of Multiprocessor Systems from Parallel Programs under Preemptive Scheduling," Proc. IEEE Int'l Conf. Reconfigurable Computing and FPGAs, Dec. 2008.
[39] D.H. Wolpert and W.G. Macready, "No Free Lunch Theorems for Optimization," IEEE Trans. Evolutionary Computation, vol. 1, no. 1, pp. 67-82, Apr. 1997.
[40] H. Ishebabi, D. Kammler, G. Ascheid, H. Meyr, O. Atak, A. Atalar, E. Arikan, M. Nicola, G. Masera, and M. Zamboni, "Design of Application Specific Processors for the Cached FFT Algorithm," Proc. IEEE Int'l Conf. Acoustics, Speech and Signal Processing (ICASSP), May 2006.
[41] P. Mahr, P. Loerchner, H. Ishebabi, and C. Bobda, "SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips," Proc. IEEE Int'l Conf. Reconfigurable Computing and FPGAs, Dec. 2008.

Index Terms:
Reconfigurable computing, chip multiprocessor systems, parallel programs.
Citation:
Harold Ishebabi, Christophe Bobda, "Heuristics for Flexible CMP Synthesis," IEEE Transactions on Computers, vol. 59, no. 8, pp. 1091-1104, Aug. 2010, doi:10.1109/TC.2010.77
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