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Issue No.08 - August (2010 vol.59)
pp: 1009-1022
Alaaeldin Amin , King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia
M. Waleed Shinwari , McMaster University, Hamilton, Ontario
ABSTRACT
This paper describes the theory and design of digital high-radix multiplier-dividers (Patent Pending). The theory of high-radix division is extended to high-radix multiplier-dividers that can perform fused multiplication and division operations using a single recurrence relation. With the fused implementation of multiplication and division, the two operations can be executed using a single instruction, implying only a single rounding operation. The recurrence relation is described, the quotient digit selection function derived, and important design parameters together with their optimal values and relations are defined. Efficient design procedure and implementation hardware are described and important system parameter values for various radix systems computed. Compared to pure dividers, the multiplier-divider requires a slightly more complex data path and quotient digit selection function.
INDEX TERMS
Computer arithmetic, division, quotient digit selection, SRT, multiplier-divider.
CITATION
Alaaeldin Amin, M. Waleed Shinwari, "High-Radix Multiplier-Dividers: Theory, Design, and Hardware", IEEE Transactions on Computers, vol.59, no. 8, pp. 1009-1022, August 2010, doi:10.1109/TC.2010.78
REFERENCES
 [1] K. Küçükçakar, "An ASIP Design Methodology for Embedded Systems," Proc. Seventh Int'l Symp. Hardware/Software Codesign (CODES '99), pp. 17-21, May 1999. [2] P. Biswas, N.D. Dutt, L. Pozzi, and P. Ienne, "Introduction of Architecturally Visible Storage in Instruction Set Extensions," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3, pp. 435-446, Mar. 2007. [3] R.E. Gonzalez, "Xtensa: A Configurable and Extensible Processor," IEEE Micro, vol. 20, no. 2, pp. 60-70, Mar./Apr. 2000. [4] J. Großschädl, "Instruction Set Extension for Long Integer Modulo Arithmetic on RISC-Based Smart Cards," Proc. 14th Symp. Computer Architecture and High Performance Computing (SBAC-PAD '02), pp. 13-19, 2002. [5] E.M. Popovici and P. Fitzpatrick, "Algorithm and Architecture for a Galois Field Multiplicative Arithmetic Processor," IEEE Trans. Information Theory, vol. 49, no. 12, pp. 3303-3307, Dec. 2003. [6] J.H.P. Zurawski and J.B. Gosling, "Design of a High-Speed Square Root Multiply and Divide Unit," IEEE Trans. Computers, vol. 36, no. 1, pp. 13-23, Jan. 1987. [7] M.D. Ercegovac and T. Lang, "Implementation of Module Combining Multiplication, Division, and Square Root," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '89), pp. 150-153, 1989. [8] R. McIlhenny and M.D. Ercegovac, "On the Implementation of a Three-Operand Multiplier," Conf. Record of the 31st Asilomar Conf. Signals, Systems & Computers, vol. 2, nos. 2-5, pp. 1168-1172, Nov. 1997. [9] E. Antelo, T. Lang, and J.D. Bruguera, "Computation of $\sqrt{X/d}$ in a Very High Radix Combined Division/Square-Root Unit with Scaling and Selection by Rounding," IEEE Trans. Computers, vol. 47, no. 2, pp. 152-161, Feb. 1998. [10] M.D. Ercegovac and T. Lang, Digital Arithmetic. Morgan Kaufmann, 2004. [11] M.D. Ercegovac and T. Lang, Division and Square Root: Digit-Recurrence Algorithms and Implementations. Kluwer Academic Publishers, 1994. [12] S.F. Obermann and M.J. Flynn, "Division Algorithms and Implementations," IEEE Trans. Computers, vol. 46, no. 8, pp. 833-854, Aug. 1997. [13] D.E. Atkins, "Higher-Radix Division Using Estimates of the Divisor and Partial Remainders," IEEE Trans. Computers, vol. 17, no. 10, pp. 925-934, Oct. 1968. [14] P. Kornerup, "Revisiting SRT Quotient Digit Selection," Proc. 16th IEEE Symp. Computer Arithmetic, pp. 38-45, June 2003. [15] P. Kornerup, "Digit Selection for SRT Division and Square Root," IEEE Trans. Computers, vol. 54, no. 3, pp. 294-303, Mar. 2005. [16] N. Takagi, "A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation," IEEE Trans. Computers, vol. 41, no. 8, pp. 949-956, Aug. 1992. [17] P.T.P. Tang, "Modular Multiplication Using Redundant Digit Division," Proc. 18th IEEE Symp. Computer Arithmetic, pp. 217-224, June 2007. [18] D. Lau, A. Schneider, M.D. Ercegovac, and J. Villasenor, "A FPGA-Based Library for On-Line Signal Processing," J. VLSI Signal Processing Systems, vol. 28, nos. 1-2, pp. 129-143, May-June 2001. [19] B. Parhami, "Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations," IEEE Trans. Computers, vol. 39, no. 1, pp. 89-98, Jan. 1990. [20] P.K.-G. Tu, "On-Line Arithmetic Algorithms for Efficient Implementation," PhD thesis, Univ. of California, Los Angeles, Sept. 1990. [21] P.K.-G. Tu and M.D. Ercegovac, "A Radix-4 On-Line Division Algorithm," Proc. IEEE Eighth Symp. Computer Arithmetic, pp. 181-187, 1987.