Issue No.07 - July (2010 vol.59)
Haohuan Fu , Stanford University, Stanford
Oskar Mencer , Imperial College London, London
Wayne Luk , Imperial College London, London
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.51
Using a general polynomial approximation approach, we present an arithmetic library generator for the logarithmic number system (LNS). The generator produces optimized LNS arithmetic libraries that improve significantly over previous LNS designs on area and latency. We also provide area cost estimation and bit-accurate simulation tools that facilitate comparison between LNS and floating-point designs.
Reconfigurable hardware, special-purpose and application-based systems, computer systems organization, computer arithmetic, general, numerical analysis, mathematics of computing.
Haohuan Fu, Oskar Mencer, Wayne Luk, "FPGA Designs with Optimized Logarithmic Arithmetic", IEEE Transactions on Computers, vol.59, no. 7, pp. 1000-1006, July 2010, doi:10.1109/TC.2010.51