Subscribe

Issue No.07 - July (2010 vol.59)

pp: 1000-1006

Haohuan Fu , Stanford University, Stanford

Oskar Mencer , Imperial College London, London

Wayne Luk , Imperial College London, London

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.51

ABSTRACT

Using a general polynomial approximation approach, we present an arithmetic library generator for the logarithmic number system (LNS). The generator produces optimized LNS arithmetic libraries that improve significantly over previous LNS designs on area and latency. We also provide area cost estimation and bit-accurate simulation tools that facilitate comparison between LNS and floating-point designs.

INDEX TERMS

Reconfigurable hardware, special-purpose and application-based systems, computer systems organization, computer arithmetic, general, numerical analysis, mathematics of computing.

CITATION

Haohuan Fu, Oskar Mencer, Wayne Luk, "FPGA Designs with Optimized Logarithmic Arithmetic",

*IEEE Transactions on Computers*, vol.59, no. 7, pp. 1000-1006, July 2010, doi:10.1109/TC.2010.51REFERENCES

- [1] E. Swartzlander, D. Chandra, H. Nagle, and S. Starks, "Sign/Logarithm Arithmetic for FFT Implementation,"
IEEE Trans. Computers, vol. 32, no. 6, pp. 526-534, June 1983.- [2] M. Arnold, T. Bailey, J. Cowles, and J. Cupal, "Redundant Logarithmic Arithmetic,"
IEEE Trans. Computers, vol. 39, no. 8, pp. 1077-1086, Aug. 1990.- [3] H. Fu, O. Mencer, and W. Luk, "Optimizing Logarithmic Arithmetic on FPGAs,"
Proc. IEEE Int'l Symp. Field-Programmable Custom Computing Machines (FCCM), pp. 163-172, 2007.- [4] M. Haselman, M. Beauchamp, K. Underwood, and K. Hemmert, "A Comparison of Floating Point and Logarithmic Number Systems for FPGAs,"
Proc. IEEE Int'l Symp. Field-Programmable Custom Computing Machines (FCCM), pp. 181-190, 2005.- [5] D. Lewis, "An Accurate LNS Arithmetic Unit Using Interleaved Memory Function Interpolator,"
Proc. Symp. Computer Arithmetic (ARITH), pp. 2-9, 1993.- [6] J. Coleman, E. Chester, C. Softley, and J. Kadlec, "Arithmetic on the European Logarithmic Microprocessor,"
IEEE Trans. Computers, vol. 49, no. 7, pp. 702-715, July 2000.- [7] B. Lee and N. Burgess, "A Parallel Look-Up Logarithmic Number System Addition/Subtraction Scheme for FPGA,"
Proc. Int'l Conf. Field-Programmable Technology (FPT), pp. 76-83, 2003.- [8] C. Chen, R. Chen, and C. Yang, "Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost,"
IEEE Trans. Computers, vol. 49, no. 7, pp. 716-726, July 2000.- [9] C. Chen and R. Chen, "Performance Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit Arithmetic,"
Proc. IEEE Int'l Conf. Application-Specific Systems, Architectures and Processors (ASAP), pp. 337-347, 2003.- [10] J. Volder, "The CORDIC Trigonometric Computing Technique,"
IRE Trans. Electronic Computing, vol. EC-8, pp. 330-334, 1959.- [11] V. Paliouras and T. Stouraitis, "A Novel Algorithm for Accurate Logarithmic Number System Subtraction,"
Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS), vol. 4, pp. 268-271, 1996.- [12] M. Arnold, "Iterative Methods for Logarithmic Subtraction,"
Proc. IEEE Int'l Conf. Application-Specific Systems, Architectures and Processors (ASAP), pp. 315-325, 2003.- [13] M. Arnold, "Improved Cotransformation for LNS Subtraction,"
Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS), vol. 2, pp. 752-755, 2002.- [14] R. Matousek, M. Tichy, Z. Pohl, J. Kadlec, C. Softley, and N. Coleman, "Logarithmic Number System and Floating-Point Arithmetic on FPGA,"
Proc. Int'l Conf. Field Programmable Logic and Applications (FPL), pp. 627-636, 2002.- [15] J. Detrey and F. Dinechin, "A Tool for Unbiased Comparison between Logarithmic and Floating-Point Arithmetic,"
J. VLSI Signal Processing, vol. 49, no. 1, pp. 161-175, Oct. 2007.- [16] J. Muller,
Elementary Functions: Algorithms and Implementation. Springer, 2006.- [17] M. Arnold and C. Walter, "Unrestricted Faithful Rounding is Good Enough for Some LNS Application,"
Proc. Symp. Computer Arithmetic (ARITH), pp. 237-246, 2001.- [18] M. Arnold, "Design of a Faithful LNS Interpolator,"
Proc. Euromicro Symp. Digital Systems Design, pp. 336-345, 2001.- [19]
Virtex-4 Family Overview, Xilinx, Inc., http:/www.xilinx.com, 2007.- [20] O. Mencer, "ASC, a Stream Compiler for Computing with FPGAs,"
IEEE Trans. Computer-Aided Design, vol. 25, no. 9, pp. 1603-1617, Sept. 2006.- [21] L. Ingber,
Adaptive Simulated Annealing (ASA) 25.15, http:/www.ingber. com, 2004.- [22] M. Gokhale, J. Frigo, C. Ahrens, J. Tripp, and R. Minnich, "Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer,"
Proc. Int'l Conf. Field Programmable Logic and Applications (FPL), pp. 95-104, 2004. |