Issue No.07 - July (2010 vol.59)
Andreas Veneris , University of Toronto, Toronto
Hratch Mangassarian , University of Toronto, Toronto
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.74
Formal CAD tools operate on mathematical models describing the sequential behavior of a VLSI design. With the growing size and state-space of modern digital hardware designs, the conciseness of this mathematical model is of paramount importance in extending the scalability of those tools, provided that the compression does not come at the cost of reduced performance. Quantified Boolean Formula satisfiability (QBF) is a powerful generalization of Boolean satisfiability (SAT). It also belongs to the same complexity class as many CAD problems dealing with sequential circuits, which makes it a natural candidate for encoding such problems. This work proposes a succinct QBF encoding for modeling sequential circuit behavior. The encoding is parametrized and further compression is achieved using time-frame windowing. Comprehensive hardware constructions are used to illustrate the proposed encodings. Three notable CAD problems, namely bounded model checking, design debugging and sequential test pattern generation, are encoded as QBF instances to demonstrate the robustness and practicality of the proposed approach. Extensive experiments on OpenCore circuits show memory reductions in the order of 90 percent and demonstrate competitive runtimes compared to state-of-the-art SAT techniques. Furthermore, the number of solved instances is increased by 16 percent. Admittedly, this work encourages further research in the use of QBF in CAD for VLSI.
SAT, QBF, BMC, k-induction, design debugging, sequential ATPG.
Andreas Veneris, Hratch Mangassarian, "Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test", IEEE Transactions on Computers, vol.59, no. 7, pp. 981-994, July 2010, doi:10.1109/TC.2010.74