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Issue No.07 - July (2010 vol.59)
pp: 905-921
Eyee Hyun Nam , Seoul National University, Seoul, Korea
Jin Hyuk Yoon , Seoul National University, Seoul, Korea
Hongseok Kim , Seoul National University, Seoul, Korea
Jin-Yong Choi , Seoul National University, Seoul, Korea
Sookwan Lee , Seoul National University, Seoul, Korea
Young Hyun Bae , Seoul National University, Seoul, Korea
Jaejin Lee , Seoul National University, Seoul, Korea
Yookun Cho , Seoul National University, Seoul, Korea
Sang Lyul Min , Seoul National University, Seoul, Korea
Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.
Flash memory, flash translation layer (FTL), solid-state disk (SSD), storage system.
Eyee Hyun Nam, Jin Hyuk Yoon, Hongseok Kim, Jin-Yong Choi, Sookwan Lee, Young Hyun Bae, Jaejin Lee, Yookun Cho, Sang Lyul Min, "Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture", IEEE Transactions on Computers, vol.59, no. 7, pp. 905-921, July 2010, doi:10.1109/TC.2010.63
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