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| Dong Kim, Kwanhu Bang, Seung-Hwan Ha, Sungroh Yoon, Eui-Young Chung, "Architecture Exploration of High-Performance PCs with a Solid-State Disk," IEEE Transactions on Computers, vol. 59, no. 7, pp. 878-890, July, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.2010.66, author = {Dong Kim and Kwanhu Bang and Seung-Hwan Ha and Sungroh Yoon and Eui-Young Chung}, title = {Architecture Exploration of High-Performance PCs with a Solid-State Disk}, journal ={IEEE Transactions on Computers}, volume = {59}, number = {7}, issn = {0018-9340}, year = {2010}, pages = {878-890}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2010.66}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Architecture Exploration of High-Performance PCs with a Solid-State Disk IS - 7 SN - 0018-9340 SP878 EP890 EPD - 878-890 A1 - Dong Kim, A1 - Kwanhu Bang, A1 - Seung-Hwan Ha, A1 - Sungroh Yoon, A1 - Eui-Young Chung, PY - 2010 KW - Solid-State Disk (SSD) KW - NAND flash memory KW - dual-port DRAM KW - North Bridge KW - direct path. VL - 59 JA - IEEE Transactions on Computers ER - | |||
[1] D. Kim, K. Bang, S.-H. Ha, C. Park, S.W. Chung, and E.-Y. Chung, "Solid-State Disk with Double Data Rate DRAM Interface for High-Performance PCs," IEICE Trans. Information and Systems, vol. E92-D, no. 4, pp. 727-731, Apr. 2009.
[2] L.-P. Chang and T.-W. Kuo, "An Adaptive Stripping Architecture for Flash Memory Storage Systems of Embedded Systems," Proc. IEEE Eighth Real-Time and Embedded Technology and Applications Symp. (RTAS), pp. 187-196, Sept. 2002.
[3] C. Park, J. Kang, S.Y. Park, and J. Kim, "Energy-Aware Demand Paging on NAND Flash-Based Embedded Storages," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED '04), pp. 338-343, 2004.
[4] J.-H. Lee, G.-H. Park, and S.-D. Kim, "A New NAND-Type Flash Memory Package with Smart Buffer System for Spatial and Temporal" J. Systems Architecture, vol. 51, pp. 111-123, Feb. 2005.
[5] S.-L. Min and E.-H. Nam, "Current Trends in Flash Memory Technology," Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 332-333, Jan. 2006.
[6] C. Park, P. Talawar, D. Won, M. Jung, J. Im, S. Kim, and Y. Choi, "A High Performance Controller for NAND Flash-Based Solid State Disk," Proc. 21st IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW), pp. 17-20, Feb. 2006.
[7] J.-U. Kang, J.-S. Kim, C. Park, H. Park, and J. Lee, "A Multi-Channel Architecture for High-Performance NAND Flash-Based Storage System" J. Systems Architecture, vol. 53, pp. 644-658, Sept. 2007.
[8] L.-P. Chang, "Hybrid Solid-State Disks: Combing Heterogeneous NAND Flash in Large SSDs," Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC '08), pp. 428-433, Mar. 2008.
[9] R. Schuetz, H. Oh, J.-K. Kim, H.-B. Pyeon, S.A. Przybylski, and P. Gillingham, "HyperLink NAND Flash Architecture for Mass Storage Applications," Proc. 22nd IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW), pp. 26-30, Aug. 2007.
[10] S. Kim, C. Park, and S. Ha, "Architecture Exploration of NAND Flash-Based Multimedia Card," Proc. Design, Automation and Test in Europe (DATE '08), pp. 218-223, Mar. 2008.
[11] J.H. Yoon, E.H. Nam, Y.J. Seong, H. Kim, B.S. Kim, S.L. Min, and Y. Cho, "Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture" IEEE Computer Architecture Letters, vol. 7, no. 1, pp. 17-20, Jan.-June 2007.
[12] J.K. Kim, H.G. Lee, S. Choi, and K.I. Bahng, "A PRAM and NAND Flash Hybrid Architecture for High-Performance Embedded Storage Subsystems," Proc. Seventh ACM Int'l Conf. Embedded Software, pp. 31-40, Oct. 2008.
[13] H. Pon and K. Rao, "A NAND Flash PC Platform Read Write Cache," Proc. 22nd IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW), pp. 21-22, Aug. 2007.
[14] Fusion IO white paper, www.fusionio.com, 2010.
[15] S.-W. Lee, B. Moon, C. Park, J.-M. Kim, and S.-W. Kim, "A Case for Flash Memory SSD in Enterprise Database Applications," Proc. ACM SIGMOD, pp. 1075-1086, 2008.
[16] T. Kgil, D. Roberts, and T. Mudge, "Improving NAND Flash Based Disk Caches," Proc. 35th Int'l Symp. Computer Architecture (ISCA), pp. 327-338, 2008.
[17] A. Caulfield, L. Grupp, and S. Swanson, "Gordon: Using Flash Memory to Build Fast, Power-Efficient Clusters for Data-Intensive Applications," Proc. 14th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 217-228, 2009.
[18] JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JEDEC Solid State Technology Assoc., 2005.
[19] H. Yang, S. Kim, H.-W. Park, J. Kim, and S. Ha, "Performance Evaluation and Optimization of Dual-Port SDRAM Architecture for Mobile Embedded Systems," Proc. Int'l Conf. Compilers, Architecture, and Synthesis for Embedded Systems (CASES '07), pp. 53-57, 2007.
[20] K. Nam, J.-S. Kim, C.S. Oh, H. Sohn, D.H. Lee, C. Lee, S. Kim, J.-W. Park, Y. Kim, M. Kim, J. Kim, H. Lee, J. Kwon, D.I. Seo, Y.-H. Jun, and K. Kim, "A 512 Mb 2-Channel Mobile DRAM (OneDRAM) with Shared Memory Array," Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC '07), pp. 204-207, 2007.
[21] IEEE Standard SystemC Language Reference Manual, 2010.
[22] Intel Corporation "Intel 965 Express Chipset Family," data sheet, July 2006.
[23] Intel Corporation "Intel I/O Controller Hub 8 (ICH8) Family," data sheet, July 2006.
[24] SATA Specification (Revision 1.0a), http:/www.serialata.org, 2010.
[25] Samsung Electronics Company, "Nand Flash Based SSD Preliminary Specification," data sheet, July 2007.
[26] R.H. Katz, G.A. Gibson, and D.A. Patterson, "Disk System Architectures for High Performance Computing" Proc. IEEE, vol. 77, no. 12, pp. 1842-1858, Dec. 1989.
[27] "ASP Comparison for 120GB HDD versus 128GB Flash-Based SSD, 2007-2012," Int'l Data Corporation (IDC), 2008.
[28] W.W. Peterson and D.T. Brown, "Cyclic Codes for Error Detection," Proc. IRE, vol. 49, pp. 228-235, Jan. 1961.

