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A Graphics Parallel Memory Organization Exploiting Request Correlations
June 2010 (vol. 59 no. 6)
pp. 762-775
ASCII Text
x 
 
George Lentaris, Dionysios Reisis, "A Graphics Parallel Memory Organization Exploiting Request Correlations," IEEE Transactions on Computers, vol. 59, no. 6, pp. 762-775, June, 2010.
 
 
BibTex
x
 
@article{ 10.1109/TC.2010.48,
author = {George Lentaris and Dionysios Reisis},
title = {A Graphics Parallel Memory Organization Exploiting Request Correlations},
journal ={IEEE Transactions on Computers},
volume = {59},
number = {6},
issn = {0018-9340},
year = {2010},
pages = {762-775},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2010.48},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - A Graphics Parallel Memory Organization Exploiting Request Correlations
IS - 6
SN - 0018-9340
SP762
EP775
EPD - 762-775
A1 - George Lentaris,
A1 - Dionysios Reisis,
PY - 2010
KW - Parallel processing
KW - graphics processors
KW - storage devices
KW - interleaved memories.
VL - 59
JA - IEEE Transactions on Computers
ER -
 
George Lentaris, National Kapodistrian University of Athens, Athens
Dionysios Reisis, National Kapodistrian University of Athens, Athens
Real-time graphics applications require memory organizations featuring parallel pixel access and low-cost implementation. This work bases on a nonlinear skew mapping scheme and exploits the correlation between consecutive requests for pixels to design an efficient parallel memory organization. The mapping achieves parallel access, of mn pixels in various shapes, to the memory organized with mn banks. The proposed design technique combines the mapping properties and the spatial correlations among pixel requests to eliminate conflicts by spending at most one extra cycle every mn consecutive parallel pixel accesses. Consequently, the technique ensures that any pixel pattern—among these commonly used in graphics—can be accessed in a single cycle from any image location. The address computations become straightforward as the numbers of the requested pixels and the banks—apart from equal—can be powers of 2.

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Index Terms:
Parallel processing, graphics processors, storage devices, interleaved memories.
Citation:
George Lentaris, Dionysios Reisis, "A Graphics Parallel Memory Organization Exploiting Request Correlations," IEEE Transactions on Computers, vol. 59, no. 6, pp. 762-775, June 2010, doi:10.1109/TC.2010.48
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