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Alvaro Vazquez, Elisardo Antelo, Paolo Montuschi, "Improved Design of HighPerformance Parallel Decimal Multipliers," IEEE Transactions on Computers, vol. 59, no. 5, pp. 679693, May, 2010.  
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@article{ 10.1109/TC.2009.167, author = {Alvaro Vazquez and Elisardo Antelo and Paolo Montuschi}, title = {Improved Design of HighPerformance Parallel Decimal Multipliers}, journal ={IEEE Transactions on Computers}, volume = {59}, number = {5}, issn = {00189340}, year = {2010}, pages = {679693}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2009.167}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Improved Design of HighPerformance Parallel Decimal Multipliers IS  5 SN  00189340 SP679 EP693 EPD  679693 A1  Alvaro Vazquez, A1  Elisardo Antelo, A1  Paolo Montuschi, PY  2010 KW  Decimal multiplication KW  parallel multiplication KW  decimal carrysave addition KW  decimal codings. VL  59 JA  IEEE Transactions on Computers ER   
[1] F.Y. Busaba, C.A. Krygowski, W.H. Li, E.M. Schwarz, and S.R. Carlough, "The IBM z900 Decimal Arithmetic Unit," Proc. Conf. Record of the Asilomar Conf. Signals, Systems and Computers, vol. 2, pp. 13351339, Nov. 2001.
[2] F.Y. Busaba, T. Slegel, S. Carlough, C. Krygowski, and J.G. Rell, "The Design of the Fixed Point Unit for the z990 Microprocessor," Proc. 14th ACM Great Lakes Symp. VLSI 2004, pp. 364367, Apr. 2004.
[3] I.D. Castellanos and J.E. Stine, "Compressor Trees for Decimal Partial Product Reduction," Proc. 18th ACM Great Lakes Symp. VLSI, pp. 107110, Mar. 2008.
[4] M. Cornea, C. Anderson, J. Harrison, P.T.P. Tang, E. Schneider, and C. Tsen, "A Software Implementation of the IEEE 754R Decimal FloatingPoint Arithmetic Using the Binary Encoding Format," Proc. 18th IEEE Symp. Computer Arithmetic, pp. 2937, June 2007.
[5] M.F. Cowlishaw, "Decimal FloatingPoint: Algorism for Computers," Proc. 16th IEEE Symp. Computer Arithmetic, pp. 104111, July 2003.
[6] M.F. Cowlishaw, The decNumber ANSI C Library, IBM Corp., 2003.
[7] M.F. Cowlishaw, E.M. Schwarz, R.M. Smith, and C.F. Webb, "A Decimal FloatingPoint Specification," Proc. 15th IEEE Symp. Computer Arithmetic, pp. 147154, June 2001.
[8] L. Dadda, "Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach," IEEE Trans. Computers, vol. 56, no. 10, pp. 13201328, Oct. 2007.
[9] L. Dadda and A. Nannarelli, "A Variant of a Radix10 Combinational Multiplier," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '08), pp. 33703373, May 2008.
[10] A.Y. Duale, M.H. Decker, H.G. Zipperer, M. Aharoni, and T.J. Bohizic, "Decimal FloatingPoint in Z9: An Implementation and Testing Perspective," IBM J. Research and Development, vol. 51, nos. 1/2, pp. 217227, Jan. 2007.
[11] L. Eisen et al., "IBM POWER6 Accelerators: VMX and DFU," IBM J. Research and Development, vol. 51, no. 6, pp. 663684, Nov. 2007.
[12] M.A. Erle and M.J. Schulte, "Decimal Multiplication via CarrySave Addition," Proc. IEEE Int'l Conf. ApplicationSpecific Systems, Architectures, and Processors, pp. 348358, June 2003.
[13] M.A. Erle, E.M. Schwarz, and M.J. Schulte, "Decimal Multiplication with Efficient Partial Product Generation," Proc. 17th IEEE Symp. Computer Arithmetic, pp. 2128, June 2005.
[14] M.A. Erle, J.M. Linebarger, and M.J. Schulte, "Potential Speedup Using Decimal FloatingPoint Hardware," Proc. 36th Asilomar Conf. Signals, Systems and Computers, pp. 10731077, Nov. 2002.
[15] M.A. Erle, M.J. Schulte, and B.J. Hickman, "Decimal FloatingPoint Multiplication via CarrySave Addition," Proc. 18th IEEE Symp. Computer Arithmetic, pp. 4655, June 2007.
[16] B.J. Hickman, A. Krioukov, M.A. Erle, and M.J. Schulte, "A Parallel IEEE P754 Decimal FloatingPoint Multiplier," Proc. 25th IEEE Conf. Computer Design, pp. 296303, Oct. 2007.
[17] IEEE Std 754(TM)2008, IEEE Standard for FloatingPoint Arithmetic, IEEE CS, Aug. 2008.
[18] R.D. Kenney and M.J. Schulte, "HighSpeed Multioperand Decimal Adders," IEEE Trans. Computers, vol. 54, no. 8, pp. 953963, Aug. 2005.
[19] R.D. Kenney, M.J. Schulte, and M.A. Erle, "HighFrequency Decimal Multiplier," Proc. IEEE Int'l Conf. Computer Design: VLSI in Computers and Processors, pp. 2629, Oct. 2004.
[20] T. Lang and A. Nannarelli, "A Radix10 Combinational Multiplier," Proc. 40th Asilomar Conf. Signals, Systems, and Computers, pp. 313317, Oct. 2006.
[21] R.H. Larson, "HighSpeed Multiply Using Four Input CarrySave Adder," IBM Technical Disclosure Bull., vol. 16, no. 7, pp. 20532054, Dec. 1973.
[22] N. Ohkubo et al., "A 4.4 ns CMOS 54x54Bit Multiplier Using PassTransistor Multiplexer," IEEE J. Solid State Circuits, vol. 30, no. 3, pp. 251256, Mar. 1995.
[23] T. Ohtsuki et al., "Apparatus for Decimal Multiplication," US Patent 4,677,583, June 1987.
[24] R.K. Richards, Arithmetic Operations in Digital Computers. D. Van Nostrand Company, Inc., 1955.
[25] M. Schmookler and A. Weinberger, "High Speed Decimal Addition," IEEE Trans. Computers, vol. 20, no. 8, pp. 862866, Aug. 1971.
[26] E.M. Schwarz, R.M. Averill,III, and L.J. Sigal, "A Radix8 CMOS S/390 Multiplier," Proc. 13th IEEE Symp. Computer Arithmetic (ARITH13 '97), pp. 29, July 1997.
[27] E.M. Schwarz, J.S. Kapernick, and M.F. Cowlishaw, "Decimal FloatingPoint Support on the IBM System z10 Processor," IBM J. Research and Development, vol. 51, no. 1, Jan./Feb. 2009.
[28] B. Shirazi, D.Y.Y. Yun, and C.N. Zhang, "RBCD: Redundant Binary Coded Decimal Adder," Proc. IEE Conf. Computers and Digital Techniques, vol. 136, pp. 156160, Mar. 1989.
[29] I.E. Sutherland, R.F. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, 1999.
[30] A. Svoboda, "Decimal Adder with SignedDigit Arithmetic," IEEE Trans. Computers, vol. 18, no. 3, pp. 212215, Mar. 1969.
[31] T. Ueda, "Decimal Multiplying Assembly and Multiply Module," US Patent 5379245, Jan. 1995.
[32] A. Vázquez and E. Antelo, "Conditional Speculative Decimal Addition," Proc. Seventh Conf. Real Numbers and Computers (RNC 7), pp. 4757, July 2006.
[33] A. Vázquez, E. Antelo, and P. Montuschi, "A New Family of HighPerformance Parallel Decimal Multipliers," Proc. 18th IEEE Symp. Computer Arithmetic, pp. 195204, June 2007.
[34] L.K. Wang, C. Tsen, M.J. Schulte, and D. Jhalani, "Benchmarks and Performance Analysis of Decimal FloatingPoint Applications," Proc. IEEE 25th Int'l Conf. Computer Design, pp. 164170, Oct. 2007.
[35] G.S. White, "Coded Decimal Number Systems for Digital Computers," Proc. Institute of Radio Engineers, vol. 41, no. 10, pp. 14501452, Oct. 1953.