Issue No.05 - May (2010 vol.59)
Hyunjin Lee , University of Pittsburgh, Pittsburgh
Sangyeun Cho , University of Pittsburgh, Pittsburgh
Bruce R. Childers , University of Pittsburgh, Pittsburgh
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2009.138
The number of CPUs in chip multiprocessors is growing at the Moore's Law rate, due to continued technology advances. However, new technologies pose serious reliability challenges, such as more frequent occurrences of degraded or even nonoperational devices, and they threaten the cost-effectiveness and dependability of future computing systems. This work studies how to protect the on-chip coherence directory from fault occurrences. In a chip multiprocessor, cache coherence mechanisms such as directory memory are critical for offering consistent data view to all CPUs. We propose a novel online fault detection and correction scheme to enhance yield and resilience to runtime errors at a small performance cost. The proposed scheme uses smart encoding and coherence protocol adaptation strategies to salvage faulty directory entries. We also develop an online error recovery scheme that protects the directory memory from soft errors. We call our fault-tolerant directory memory architecture PERFECTORY. Evaluation results show that PERFECTORY achieves very high fault resilience: Over 99 percent chip yield at 0.05 percent hard error ratio and 1,934 years MTTF at 1,000 FIT using a 100-processor cluster configuration. PERFECTORY limits performance degradation to less than 1 percent at 0.05 percent hard error ratio and requires significantly smaller area overheads than existing redundancy approaches.
Chip multiprocessor, cache coherence, chip yield, lifetime reliability.
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers, "PERFECTORY: A Fault-Tolerant Directory Memory Architecture", IEEE Transactions on Computers, vol.59, no. 5, pp. 638-650, May 2010, doi:10.1109/TC.2009.138