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Issue No.04 - April (2010 vol.59)
pp: 532-544
Wu Jigang , Tianjin Polytechnic University, China and Nanyang Technological University, Singapore
Thambipillai Srikanthan , Nanyang Technological University, Singapore
Guang Chen , Nortel Networks and Peking University, Beijing
Hardware/software (HW/SW) partitioning is one of the key challenges in HW/SW codesign. This paper presents efficient algorithms for the HW/SW partitioning problem, which has been proved to be NP-hard. We reduce the HW/SW partitioning problem to a variation of knapsack problem that is approximately solved by searching 1D solution space, instead of searching 2D solution space in the latest work cited in this paper, to reduce time complexity. Three heuristic algorithms are proposed to determine suitable partitions to satisfy HW/SW partitioning constraints. We have shown that the time complexity for partitioning a graph with n nodes and m edges is significantly reduced from O(d_{x}\cdot d_{y}\cdot n^{3}) to O(n\log n + d\cdot (n+m)), where d and d_{x}\cdot d_{y} are the number of the fragments of the searched 1D solution space and the searched 2D solution space, respectively. The lower bound on the solution quality is also proposed based on the new computing model to show that it is comparable to that reported in the literature. Moreover, empirical results show that the proposed algorithms produce comparable and often better solutions when compared to the latest algorithm while reducing the time complexity significantly.
Hardware/software partitioning, heuristic, algorithm, complexity, knapsack problem.
Wu Jigang, Thambipillai Srikanthan, Guang Chen, "Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms", IEEE Transactions on Computers, vol.59, no. 4, pp. 532-544, April 2010, doi:10.1109/TC.2009.173
[1] J. Staunstrup and W.H. Wolf, Hardware/Software Co-Design: Principles and Practice. Kluwer, 1997.
[2] D. Gajski, F. Vahid, S. Narayan, and J. Gong, "Specsyn: An Environment Supporting the Specify-Explorerefine Paradigm for Hardware/Software System Design," IEEE Trans. Very Large Scale Integration Systems, vol. 6, no. 1, pp. 84-100, Mar. 1998.
[3] J. Henkel, "A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems," Proc. Design Automation Conf., pp. 122-127, , 1999.
[4] M. O'Nils, A. Jantsch, A. Hemani, and H. Tenhunen, "Interactive Hardware-Software Partitioning and Memory Allocation Based on Data Transfer Profiling," Proc. Int'l Conf. Recent Advances in Mechatronics, pp. 447-452, 476586.html, 1995.
[5] J. Madsen et al., "Lycos: The Lyngby Cosynthesis System," Design Automation for Embedded Systems, vol. 2, no. 2, pp. 195-235, 1997.
[6] R. Niemann and P. Marwedel, "An Algorithm for Hardware/Software Partitioning Using Mixed Integer Linear Programming," Design Automation for Embedded Systems, vol. 2, pp. 165-193, 1997.
[7] M. Weinhardt, "Integer Programming for Partitioning in Software Oriented Codesign," Proc. Fifth Int'l Workshop Field-Programmable Logic and Applications (FPL '95), pp. 227-234, 1995.
[8] K.S. Chatha and R. Vemuri, "Hardware-Software Partitioning and Pipelined Scheduling of Transformative Applications," IEEE Trans. Very Large Scale Integration Systems, vol. 10, no. 3, pp. 193-208, June 2002.
[9] A. Kalavade, "System-Level Codesign of Mixed Hardware-Software Systems," PhD dissertation, EECS Dept., Univ. of California, Berkeley, 19952894.html, 1995.
[10] R. Niemann and P. Marwedel, "Hardware/Software Partitioning Using Integer Programming," Proc. European Design and Test Conf., pp. 473-480, 1996.
[11] R.K. Gupta and G.D. Micheli, "Hardware-Software Cosynthesis for Digital Systems," IEEE Design and Test of Computers, vol. 10, no. 3, pp. 29-41, Sept. 1993.
[12] F. Vahid, D.D. Gajski, and J. Gong, "A Binary-Constraint Search Algorithm for Minimizing Hardware During Hardware/Software Partitioning," Proc. Conf. European Design Automation (EURO-DAC '94), pp. 214-219, 1994.
[13] F. Vahid and D.D. Gajski, "Clustering for Improved System-Level Functional Partitioning," Proc. Eighth Int'l Symp. System Synthesis (ISSS '95), pp. 28-35, 1995.
[14] G. Quan, X. Hu, and G.W. Greenwood, "Preference-Driven Hierarchical Hardware/Software Partitioning," Proc. 1999 IEEE Int'l Conf. Computer Design (ICCD '99), pp. 652-657, 1999.
[15] V. Srinivasan, S. Radhakrishnan, and R. Vemuri, "Hardware/Software Partitioning with Integrated Hardware Design Space Exploration," Proc. Conf. Design, Automation and Test in Europe (DATE '98), pp. 28-35, 1998.
[16] R.P. Dick and N.K. Jha, "MOGAC: A Multiobjective Genetic Algorithm for Hardware-Software Co-Synthesis of Hierarchical Heterogeneous Distributed Embedded Systems," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 10, pp. 920-935, Oct. 1998.
[17] Z. Peng and K. Kuchcinski, "An Algorithm for Partitioning of Application Specific Systems," Proc. European Conf. Design Automation (EDAC '93), pp. 316-321, html , 1993.
[18] J. Henkel and R. Ernst, "An Approach to Automated Hardware/Software Partitioning Using a Flexible Granularity That Is Driven by High-Level Estimation Techniques," IEEE Trans. Very Large Scale Integration Systems, vol. 9, no. 2, pp. 273-290, Apr. 2001.
[19] P. Eles, Z. Peng, K. Kuchcinski, and A. Doboli, "System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search," Design Automation for Embedded Systems, vol. 2, pp. 5-32, 1997.
[20] R. Ernst, J. Henkel, and T. Benner, "Hardware-Software Cosynthesis for Microcontrollers," IEEE Design and Test of Computers, vol. 10, no. 4, pp. 64-75, Dec. 1993.
[21] T. Wiangtong, P.Y.K. Cheung, and W. Luk, "Comparing Three Heuristic Search Methods for Functional Partitioning in Hardwaresoftware Codesign," Design Automation for Embedded Systems, vol. 6, no. 4, pp. 425-449, 2002.
[22] K.S. Chatha and R. Vemuri, "Magellan: Multiway Hardware-Software Partitioning and Scheduling for Latency Minimization of Hierarchical Control-Dataflow Task Graphs," Proc. Ninth Int'l Symp. Hardware/Software Codesign (CODES '01), pp. 42-47, 2001.
[23] J. Grode, P.V. Knudsen, and J. Madsen, "Hardware Resource Allocation for Hardware/Software Partitioning in the LycosSystem," Proc. Conf. Design, Automation and Test in Europe (DATE '98), pp. 22-27, 1998.
[24] A. Kalavade and E.A. Lee, "The Extended Partitioning Problem: Hardware/Software Mapping, Scheduling, and Implementation-Bin Selection," Design Automation for Embedded Systems, vol. 2, no. 2, pp. 125-163, 1997.
[25] A. Kalavade and P.A. Subrahmanyam, "Hardware/Software Partitioning for Multifunction Systems," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 9, pp. 819-837, Sept. 1998.
[26] M.L. Lopez, C.A Iglesias, and J.C. Lopez, "A Knowledge-Based System for Hardware-Software Partitioning," Proc. Conf. Design, Automation and Test in Europe (DATE '98), pp. 914-915, 1998.
[27] M. Lopez-Vallejo and J.C. Lopez, "On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques," ACM Trans. Design Automation of Electronic Systems, vol. 8, no. 3, pp. 269-297, 2003.
[28] W.H. Wolf, "An Architectural Co-Synthesis Algorithm for Distributed, Embedded Computing Systems," IEEE Trans. Very Large Scale Integration Systems, vol. 5, no. 2, pp. 218-229, June 1997.
[29] T.F. Abdelzaher and K.G. Shin, "Period-Based Load Partitioning and Assignment for Large Real-Time Applications," IEEE Trans. Computers, vol. 49, no. 1, pp. 81-87, Jan. 2000.
[30] Y.G. Saab, "A Fast and Robust Network Bisection Algorithm," IEEE Trans. Computers, vol. 44, no. 7, pp. 903-913, July 1995.
[31] P. Arato, Z.A. Mann, and A. Orban, "Algorithmic Aspects of Hardware/Software Partitioning," ACM Trans. Design Automation of Electronic Systems, vol. 10, no. 1, pp. 136-156, 2005.
[32] H. Lee and P.S. Pulat, "Bicriteria Network Flow Problems: Continuous Case," European J. Operational Research, vol. 51, no. 1, pp. 119-126, Mar. 1991.
[33] H. Lee and P.S. Pulat, "Bicriteria Network Flow Problems: Integer Case," European J. Operational Research, vol. 66, no. 1, pp. 148-157, Apr. 1993.
[34] M.V. Marathe, R. Ravi, R. Sundaram, and S.S. Ravi, "Bicriteria Network Design Problems," J. Algorithms, vol. 28, pp. 487-498, 1998.
[35] A. Sedeńo-Noda and C. González-Martín, "An Algorithm for the Biobjective Integer Minimum Cost Flow Problem," Computers and Operations Research, vol. 28, no. 2, pp. 139-156, 2001.
[36] M. Gen, L. Lin, and R. Cheng, "Bicriteria Network Optimization Problem Using Priority-Based Genetic Algorithm," IEEJ Trans. Electronics, Information, and Systems, vol. 124, no. 10, pp. 1972-1978, 2004.
[37] H.W. Hamacher, C.R. Pedersen, and S. Ruzika, "Multiple Objective Minimum Cost Flow Problems: A Review," European J. Operational Research, vol. 176, no. 3, pp. 1404-1422, Feb. 2007.
[38] W. Jigang and T. Srikanthan, "Low-Complex Dynamic Programming Algorithm for Hardware/Software Partitioning," Information Processing Letters, vol. 98, no. 2, pp. 41-46, 2006.
[39] M.D. Galanis, G. Dimitroulakos, A.P. Kakarountas, and C.E. Goutis, "Speedups from Partitioning Software Kernels to fpga Hardware in Embedded Socs," Proc. IEEE Workshop Signal Processing Systems Design and Implementation, pp. 485-490, 2005.
[40] G. Stitt, F. Vahid, and S. Nematbakhsh, "Energy Savings and Speedups from Partitioning Critical Software Loops to Hardware in Embedded Systems," Trans. Embedded Computing Systems, vol. 3, no. 1, pp. 218-232, 2004.
[41] K. Daniel and S. Natasha, "Formal Verification of SystemC by Automatic Hardware/Software Partitioning," Proc. Conf. Formal Methods and Programming Models for Codesign (MEMOCODE '05), pp. 101-110, 2005.
[42] L. Silva, A. Sampaio, and E. Barros, "A Constructive Approach to Hardware/Software Partitioning," Formal Methods in System Design, vol. 24, no. 1, pp. 45-90, 2004.
[43] S. Sirowy, Y. Wu, S. Lonardi, and F. Vahid, "Two-Level Microprocessor-Accelerator Partitioning," Proc. Conf. Design, Automation and Test in Europe (DATE '07), pp. 313-318, 2007.
[44] S. Sirowy and F. Vahid, "Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning," Proc. Int'l Embedded Systems Symp. (IESS '07), Embedded System Design: Topics, Techniques and Trends, pp. 145-154, 2007.
[45] P. Arato, S. Juhasz, Z.A. Mann, A. Orban, and D. Papp, "Hardware-Software Partitioning in Embedded System Design," Proc. IEEE Int'l Symp. Intelligent Signal Processing, pp. 197-202, 2003.
[46] A.V. Goldberg and R.E. Tarjan, "A New Approach to the Maximum-Flow Problem," J. ACM, vol. 35, no. 4, pp. 921-940, 1988.
[47] B.V. Cherkassky and A.V. Goldberg, "On Implementing the Push-Relabel Method for the Maximum Flow Problem," Algorithmica, vol. 19, no. 4, pp. 390-410, 1997.
[48] C. Chekuri and S. Khanna, "A Polynomial Time Approximation Scheme for the Multiple Knapsack Problem," SIAM J. Computing, vol. 35, no. 3, pp. 713-728, 2005.
[49] S. Martello and P. Toth, Knapsack Problems: Algorithms and Computer Implementations. John Wiley & Sons, Inc., 1990.
[50] R. Beier, B.V. Ocking, and F. Informatik, "Probabilistic Analysis of Knapsack Core Algorithms," Proc. 14th Ann. ACM-SIAM Symp. Discrete Algorithms, pp. 461-470, 2004.
[51] H. Nagamochi and T. Ibaraki, "Computing Edge-Connectivity in Multigraphs and Capacitated Graphs," SIAM J. Discrete Math., vol. 5, no. 1, pp. 54-66, 1992.
[52] D.E. Knuth, The Art of Computer Programming, Volume 3: Sorting and Searching, second version. Addison-Wesley, 1998.
[53] M. Guthaus et al., "Mibench: A Free, Commercially Representative Embedded Benchmark Suite," Proc. Fourth IEEE Int'l Workshop Workload Characteristics, pp. 3-14, Dec. 2001.
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