Issue No.04 - April (2010 vol.59)
Yung-Chieh Lin , National Cheng Kung University, Tainan
Yeim-Kuan Chang , National Cheng Kung University, Tainan
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2009.153
A dynamic multiway segment tree (DMST) is proposed for IP lookups in this paper. DMST is designed for dynamic routing tables that can dynamically insert and delete prefixes. DMST is implemented as a B-tree that has all distinct end points of ranges as its keys. The complexities of search, insertion, deletion, and memory requirement are the same as the existing multiway range tree (MRT) and prefix in B-tree (PIBT) for prefixes. In addition, a pipelined DMST search engine is proposed to further speed up the search operations. The proposed pipelined DMST search engine uses off-chip SRAMs instead of on-chip SRAMs because the capacity of the latter is too small to hold large routing tables and the cost of the latter is too expensive. By utilizing current FPGA and off-chip SRAM technologies, our proposed five-stage pipelined search engine can achieve the worst case throughputs of 33.3 and 41.7 million packets per second (Mpps) with 144-bit and 288-bit wide SRAM blocks, respectively. Furthermore, a straightforward extension of the pipelined search engine with multiple independent off-chip SRAMs can achieve the throughput of 200 Mpps which is equivalent to 102 Gbps for minimal Ethernet packets of size 64 bytes.
Segment tree, elementary interval, B-tree, pipeline, FPGA.
Yung-Chieh Lin, Yeim-Kuan Chang, "Dynamic Multiway Segment Tree for IP Lookups and the Fast Pipelined Search Engine", IEEE Transactions on Computers, vol.59, no. 4, pp. 492-506, April 2010, doi:10.1109/TC.2009.153