The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.12 - December (2009 vol.58)
pp: 1710-1725
Dragan Jankovi? , Faculty of Electronics, Niš
Radomir S. Stankovi? , Faculty of Electronics, Niš
Claudio Moraga , European Centre for Soft Computing, Mieres
ABSTRACT
Reed-Muller expressions and their various extensions and generalizations for binary and multiple-valued logic functions are an important class of discrete function representations that are often used in practical applications. These expressions can be uniformly viewed as discrete polynomial expressions over finite fields GF(2) and GF(q) or the field of rational numbers in the case of expressions with integer-valued coefficients. The optimization of them in the number of product terms count is performed by selecting either positive or negative literals (polarities) for variables in the functions to be represented. Since there are no ways to select in advance the polarity for variables that will result in most compact expression for a given function, all possible expressions have to be generated and the simplest of them selected. This is a task computationally very demanding, the complexity of which is O(q^n \times C), where C is the time to calculate a particular polarity. Since the reduction of the first factor may lead to missing the most compact expression, the reduction of C is the single option to speed up the procedure. In this paper, we propose an approach to the solution of this problem by exploiting the notion of extended dual polarity, which provides a simple way of ordering polarities to obtain an effective way of finding the optimal one by reducing the time to move between them. The method still implies exhaustive search, but it is an optimized search, which may be expressed in very simple rules resulting in efficient implementation. Experimental results illustrate the effectiveness of the proposed method.
INDEX TERMS
Switching functions, multiple-valued functions, Reed-Muller expressions, polynomial expressions, fixed-polarity expressions.
CITATION
Dragan Jankovi?, Radomir S. Stankovi?, Claudio Moraga, "Optimization of Polynomial Expressions by Using the Extended Dual Polarity", IEEE Transactions on Computers, vol.58, no. 12, pp. 1710-1725, December 2009, doi:10.1109/TC.2009.113
REFERENCES
[1] G.D. De Micheli, R. Brayton, and A. Sangiovanni-Vincentelli, “Optimal State Assignment for Finite State Machines,” IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, vol. 4, no. 3, pp. 269-284, July 1985.
[2] R. Drechsler, H. Hengster, H. Schaefer, J. Hartman, and B. Becker, “Testability of 2-Level AND/EXOR Circuits,” J. Electronic Testing, Theory and Application, vol. 14, no. 3, pp. 173-192, 1999.
[3] E. Dubrova, “Multiple-Valued Logic Synthesis and Optimization,” Logic Synthesis and Verification, S. Hassoun and T. Sasao, eds., pp.89-114, Kluwer Academic Publishers, 2002.
[4] E. Dubrova and P. Farm, “A Conjunctive Canonical Expansion of Multiple-Valued Functions,” Proc. 32nd IEEE Int'l Symp. Multiple-Valued Logic, pp.15-18, May 2002.
[5] E.V. Dubrova and J.C. Muzio, “Generalized Reed-Muller Canonical Form for a Multiple-Valued Algebra,” Multiple-Valued Logic, vol. 1, pp. 65-84, 1996.
[6] E. Dubrova and H. Sack, “Probabilistic Verification of Multiple-Valued Functions,” Proc. 30th Int'l Symp. Multiple-Valued Logic, pp. 23-25, May 2000.
[7] B.J. Falkowski and F. Cheng, “Family of Fast Transforms over GF(3) Logic,” Proc. 33rd Int'l Symp. Multiple-Valued Logic, pp. 16-19, May 2003.
[8] B.J. Falkowski and C.-H. Chang, “Optimization of Partially-Mixed-Polarity Reed-Muller Expansions,” Proc. Int'l Symp. Circuits and Systems (ISCAS '99), vol. 1, pp. 383-386, May/June 1999.
[9] B.J. Falkowski and S. Rahardja, “Efficient Computation of Quaternary Fixed Polarity Reed-Muller Expansions,” IEE Proc. Computers and Digital Techniques, vol. 142, no. 5, pp. 345-352, Sept. 1995.
[10] P. Farm, E. Dubrova, R.S. Stanković, and J. Astola, “Conjunctive Decomposition for Multiple-Valued Input Binary-Valued Output Functions,” Proc. TISCP Workshop Spectral Methods and Multirate Signal Processing (SMMSP '02), pp. 227-234, Sept. 2002.
[11] M. Gao, J.-H. Jiang, Y. Jiang, Y. Li, S. Sinha, and R. Brayton, “MVSIS,” Proc. Int'l Workshop Logic Synthesis, pp. 138-144, June 2001.
[12] M.R. Garey and D.S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. N.Y. Freeman, 1979.
[13] D.H. Green, “Dual Forms of Reed-Muller Expansions,” IEE Proc. Computers and Digital Techniques, vol. 141, no. 3, pp. 184-192, 1994.
[14] A.M. Jabir, D. Pradhan, and J. Mathew, “GfXpress: A Technique for Synthesis and Optimization of GF($2^{m}$ ) Polynomials,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 4, pp. 698-711, Apr. 2008.
[15] A.M. Jabir, D. Pradhan, and J. Mathew, “An Efficient Technique for Synthesis and Optimization of Polynomials in GF($2^{m}$ ),” Proc. IEEE Int'l Conf. Computer Aided Design, pp. 151-157, Nov. 2006.
[16] D. Janković, “Tabular Technique for the Fixed Polarity Arithmetic Transform Calculation,” Proc. Electronics, Telecomm., Computers and Nuclear Eng. Conf. (ETRAN), 2003.
[17] D. Janković, R.S. Stanković, and R. Drechsler, “Cube Tabular Technique for Calculation of Fixed Polarity Reed-Muller Expressions and Applications,“ Proc. Workshop Computational Intelligence and Informational Technologies, pp. 81-88, June 2001.
[18] D. Janković, R.S. Stanković, and R. Drechsler, “Efficient Calculation of Fixed Polarity Polynomial Expressions for Multi-Valued Logic Function,” Proc. 32nd Int'l Symp. Multiple-Valued Logic, pp.76-82, May 2002.
[19] D. Janković, R.S. Stanković, and C. Moraga, “Optimization of Kronecker Expressions Using the Extended Dual Polarity Property,” Proc. XXXVII Int'l Scientific Conf. Information, Comm. and Energy Systems and Technologies (ICEST), pp. 749-752, 2002.
[20] D. Janković, R.S. Stanković, and C. Moraga, “Optimization of GF(4) Expressions Using the Extended Dual Polarity Property,” Proc. 33rd Int'l Symp. Multiple-Valued Logic, pp. 50-56, May 2003.
[21] D. Janković, R.S. Stanković, and C. Moraga, “Optimization of Arithmetic Expressions Using the Dual Polarity Property,” Proc. First Balkan Conf. Informatics (BCI '03), pp. 402-410, Nov. 2003.
[22] D. Janković, R.S. Stanković, and C. Moraga, ”Arithmetic Expressions Optimization Using Dual Polarity Property,” Serbian J. Electrical Eng., vol. 1, no. 1, pp. 71-80, Nov. 2003.
[23] M.G. Karpovsky, R.S. Stanković, and C. Moraga, “Spectral Techniques in Binary and Multiple-Valued Switching Theory. A Review of Results in the Decade 1991-2000,” Proc. 31st Int'l Symp. Multiple-Valued Logic, pp. 41-46, May 2001.
[24] J.C. Muzio and T.C. Wesselkamper, Multiple-Valued Switching Theory. Adam Hilger, 1986.
[25] D. Pradhan, “A Theory of Galois Switching Functions,” IEEE Trans. Computers, vol. 27, no. 3, pp. 239-248, Mar. 1978.
[26] D. Pradhan, A. Singh, T. Rajaprabhu, and A.M. Jabir, “Switching Theory: A Uniform Framework for Multi-Level Verification,” Proc. 14th Int'l Workshop Logic and Synthesis, June 2005.
[27] S. Rahardja and B.J. Falkowski, “Efficient Algorithm to Calculate Reed-Muller Expansions over $GF$ (4),” IEE Proc. Circuits, Devices and Systems, vol. 148, no. 6, pp. 289-295, 2001.
[28] S.M. Reddy, “Easily Testable Realizations for Logic Functions,” IEEE Trans. Computers, vol. 21, no. 11, pp. 1183-1188, Nov. 1972.
[29] R. Rudel and A. Sangiovanni-Vincentelli, “Multiple-Valued Minimization for PLA Optimization,” IEEE Trans. CAD/ICAS, vol. 5, no. 9, pp. 727-750, Sept. 1987.
[30] A. Sarabi and M.A. Perkowski, “Fast Exact and Quasi-Minimal Minimization of Highly Testable Fixed Polarity AND/XOR Canonical Networks,” Proc. 29th Design Automation Conf., pp.30-35, June 1992.
[31] T. Sasao, “Multiple-Valued Logic and Optimization of Programmable Logic Arrays,” IEEE Trans. Computers, vol. 21, no. 4, pp. 71-80, Apr. 1988.
[32] T. Sasao, “EXMIN—a Simplification Algorithm for Exclusive-or-Sum-of-Product Expressions for Multiple-Valued Input Two-Valued Output Functions,” Proc. 20th Int'l Symp. Multiple-Valued Logic, pp. 128-135, May 1990.
[33] T. Sasao, “A Transformation of Multiple-Valued Input Two-Valued Output Functions and Its Application to Simplification of Exclusive-or-Sum-of-Products Expressions,” Proc. 21st Int'l Symp. Multiple-Valued Logic, pp. 270-279, May 1991.
[34] T. Sasao, “Easily Testable Realizations for Generalized Reed-Muller Expressions,” IEEE Trans. Computers, vol. 46, no. 6, pp.709-716, June 1997.
[35] T. Sasao, Switching Theory for Logic Synthesis. Kluwer Academic Publishers, 1999.
[36] T. Sasao and J.T. Butler, “A Design Method for Look-Up Table Type FPGA by Pseudo-Kronecker Expansions,” Proc. 24th Int'l Symp. Multiple-Valued Logic, pp. 97-104, May 1994.
[37] R.S. Stanković, Spectral Transform Decision Diagrams in Simple Questions and Simple Answers. Nauka, 1998.
[38] R.S. Stanković, D. Janković, and C. Moraga, “Reed-Muller-Fourier versus Galois Field Representations of Four-Valued Logic Functions,” Proc. 28th Int'l Symp. Multiple-Valued Logic, pp. 186-191, May 1998.
[39] R.S. Stanković and C. Moraga, “Reed-Muller-Fourier Representations of Multiple-Valued Functions over Galois Fields of Prime Cardinalty,” U. Kebschull, E. Schubert, and W. Rosensteil, eds., Proc. IFIP WG 10.5 Workshop Applications of the Reed-Muller Expansion in Circuit Design, pp. 115-124, 1993.
[40] E.C. Tan and H. Yang, “Fast Tabular Technique for Fixed-Polarity Reed-Muller Logic with Inherent Parallel Processes,” Int'l J. Electronics, vol. 85, no. 85, pp. 511-520, 1998.
[41] E.C. Tan and H. Yang, “Optimization of Fixed-Polarity Reed-Muller Circuits Using Dual-Polarity Property,” Circuits Systems Signal Process, vol. 19, no. 6, pp. 535-548, 2000.
[42] C. Tsai and M. Marek-Sadowska, “Generalized Reed-Muller Forms as a Tool to Detect Symmetries,” IEE Proc. Computers and Digital Techniques, vol. 141, no. 6, pp. 369-374, Nov. 1994.
[43] C. Tsai and M. Marek-Sadowska, “Boolean Functions Classification via Fixed Polarity Reed-Muller Forms,” IEEE Trans. Computers, vol. 46, no. 2, pp. 173-186, Feb. 1997.
[44] C.S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Trans. Computers, vol. 13, no. 1, pp. 14-17, Feb. 1964.
19 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool