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A Complexity-Effective Out-of-Order Retirement Microarchitecture
December 2009 (vol. 58 no. 12)
pp. 1626-1639
ASCII Text
x 
 
Salvador Petit Martí, Julio Sahuquillo Borrás, Pedro López Rodríguez, Rafael Ubal Tena, José Duato Marín, "A Complexity-Effective Out-of-Order Retirement Microarchitecture," IEEE Transactions on Computers, vol. 58, no. 12, pp. 1626-1639, December, 2009.
 
 
BibTex
x
 
@article{ 10.1109/TC.2009.95,
author = {Salvador Petit Martí and Julio Sahuquillo Borrás and Pedro López Rodríguez and Rafael Ubal Tena and José Duato Marín},
title = {A Complexity-Effective Out-of-Order Retirement Microarchitecture},
journal ={IEEE Transactions on Computers},
volume = {58},
number = {12},
issn = {0018-9340},
year = {2009},
pages = {1626-1639},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2009.95},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - A Complexity-Effective Out-of-Order Retirement Microarchitecture
IS - 12
SN - 0018-9340
SP1626
EP1639
EPD - 1626-1639
A1 - Salvador Petit Martí,
A1 - Julio Sahuquillo Borrás,
A1 - Pedro López Rodríguez,
A1 - Rafael Ubal Tena,
A1 - José Duato Marín,
PY - 2009
KW - Instruction-level parallelism
KW - out-of-order commit
KW - long latency operations
KW - control dependencies
KW - exception handling.
VL - 58
JA - IEEE Transactions on Computers
ER -
 
Salvador Petit Martí, Universidad Politécnica de Valencia, Spain
Julio Sahuquillo Borrás, Universidad Politécnica de Valencia, Spain
Pedro López Rodríguez, Universidad Politécnica de Valencia, Spain
Rafael Ubal Tena, Universidad Politécnica de Valencia, Spain
José Duato Marín, Universidad Politécnica de Valencia, Spain
Current superscalar processors commit instructions in program order by using a reorder buffer (ROB). The ROB provides support for speculation, precise exceptions, and register reclamation. However, committing instructions in program order may lead to significant performance degradation if a long latency operation blocks the ROB head. Several proposals have been published to deal with this problem. Most of them retire instructions speculatively. However, as speculation may fail, checkpoints are required in order to rollback the processor to a precise state, which requires both extra hardware to manage checkpoints and the enlargement of other major processor structures, which, in turn, might impact the processor cycle. This paper focuses on out-of-order commit in a nonspeculative way, thus, avoiding checkpointing. To this end, we replace the ROB with a validation buffer (VB) structure. This structure keeps dispatched instructions until they are nonspeculative or mispeculated, which allows an early retirement. By doing so, the performance bottleneck is largely alleviated. An aggressive register reclamation mechanism targeted to this microarchitecture is also devised. As experimental results show, the VB structure is much more efficient than a typical ROB since, with only 32 entries, it achieves a performance close to an in-order commit microprocessor using a 256-entry ROB.

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Index Terms:
Instruction-level parallelism, out-of-order commit, long latency operations, control dependencies, exception handling.
Citation:
Salvador Petit Martí, Julio Sahuquillo Borrás, Pedro López Rodríguez, Rafael Ubal Tena, José Duato Marín, "A Complexity-Effective Out-of-Order Retirement Microarchitecture," IEEE Transactions on Computers, vol. 58, no. 12, pp. 1626-1639, Dec. 2009, doi:10.1109/TC.2009.95
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