This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures
November 2009 (vol. 58 no. 11)
pp. 1553-1567
Siavash Bayat-Sarmadi, Univeristy of Waterloo, Waterloo
M. Anwar Hasan, University of Waterloo, Waterloo
In this work, we consider detection of errors in polynomial, dual, and normal bases arithmetic operations. Error detection is performed by recomputing with the shifted operand method, while the operation unit is in use. This scheme is efficient for pipelined architectures, particularly systolic arrays. Additionally, one semisystolic multiplier for each of the polynomial, dual, type I, and type II optimal normal bases is presented. The results show that for having better or similar space and time overheads compared to a number of related previous work, the multipliers have generally a higher error-detection capability, e.g., the error-detection capability of the RESO-based scheme for single and multiple stuck-at faults in a polynomial basis multiplier is 100 percent. Finally, we also comment on how RESO can be used for concurrent error correction to deal with transient faults.

[1] I. Biehl, B. Meyer, and V. Muller, “Differential Fault Attacks on Elliptic Curve Cryptosystems,” Proc. 20th Int'l Conf. Cryptography, pp. 131-146, 2000.
[2] J. Blomer, M. Otto, and J.P. Seifert, “Sign Change Fault Attacks on Elliptic Curve Cryptosystems,” Proc. Third Workshop Fault Tolerance and Diagnosis in Cryptography (FTDC), pp. 36-52, 2006.
[3] D. Boneh, R. DeMillo, and R. Lipton, “On the Importance of Checking Cryptographic Protocols for Faults,” Proc. Eurocrypt, pp.37-51, 1997.
[4] M. Ciet and M. Joye, “Elliptic Curve Cryptosystems in the Presence of Permanent and Transient Faults,” Designs, Codes, and Cryptography, vol. 36, no. 1, pp. 33-43, July 2005.
[5] S.B. Wicker and V.K. Bhargava, Reed-Solomon Codes and Their Applications. John Wiley & Sons, Inc., 1999.
[6] D. Pradhan and M. Chatterjee, “GLFSR—A New Test Pattern Generator for Built-in-Self-Test,” Proc. Int'l Test Conf., pp. 481-490, 1994.
[7] D.A. McGrew and J. Viega, “The Galois/Counter Mode of Operation (GCM),” Proc. NIST Symmetric Key Block Ciphers Modes of Operation Workshop, 2005.
[8] T. Elgamal, “A Public Key Cryptosystem and a Signature Scheme Based on Discrete Logarithms,” IEEE Trans. Information Theory, vol. 31, no. 4, pp. 469-472, July 1985.
[9] G. Bertoni, L. Breveglieri, I. Koren, P. Maistri, and V. Piuri, “Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard,” IEEE Trans. Computers, vol. 52, no. 4, pp. 1-14, Apr. 2003.
[10] C.W. Chiou, “Concurrent Error Detection in Array Multipliers for $GF(2^m)$ Fields,” Electronics Letters, vol. 38, no. 14, pp. 688-689, July 2002.
[11] N. Joshi, K. Wu, and R. Karri, “Concurrent Error Detection for Involutional Functions with Applications in Fault-Tolerant Cryptographic Hardware Design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 6, pp. 1163-1169, June 2006.
[12] S. Bayat-Sarmadi and M.A. Hasan, “On Concurrent Detection of Errors in Polynomial Basis Multiplication,” IEEE Trans. Very Large Scale Integration, vol. 15, no. 4, pp. 413-426, Apr. 2007.
[13] S. Bayat-Sarmadi and M.A. Hasan, “Detecting Errors in a Polynomial Basis Multiplier Using Multiple Parity Bits for Both Inputs,” Proc. 25th Int'l Conf. Computer Design (ICCD), pp. 368-375, 2007.
[14] S. Fenn, M. Gossel, M. Benaissa, and D. Taylor, “Online Error Detection for Bit-Serial Multipliers in ${GF}(2^m)$ ,” J. Electronics Testing: Theory and Applications, vol. 13, pp. 29-40, 1998.
[15] A. Reyhani-Masoleh and M.A. Hasan, “Error Detection in Polynomial Basis Multipliers over Binary Extension Fields,” Proc. Fourth Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES), pp. 515-528, 2002.
[16] A. Reyhani-Masoleh and M.A. Hasan, “Towards Fault-Tolerant Cryptographic Computations over Finite Fields,” ACM Trans. Embedded Computer Systems, vol. 3, no. 3, pp. 593-613, Aug. 2004.
[17] A. Reyhani-Masoleh and M.A. Hasan, “Fault Detection Architectures for Field Multiplication Using Polynomial Bases,” IEEE Trans. Computers, special issue on fault diagnosis and tolerance in cryptography, vol. 55, no. 9, pp. 1089-1103, Sept. 2006.
[18] S. Bayat-Sarmadi and M.A. Hasan, “Run-Time Error Detection of Polynomial Basis Multiplication Using Linear Codes,” Proc. 18th Int'l Conf. Application-Specific Systems, Architectures and Processors (ASAP), pp. 204-209, 2007.
[19] G. Gaubatz and B. Sunar, “Robust Finite Field Arithmetic for Fault-Tolerant Public-Key Cryptography,” Proc. Third Workshop Fault Tolerance and Diagnosis in Cryptography (FTDC), pp. 196-210, 2006.
[20] G. Gaubatz, B. Sunar, and M.G. Karpovsky, “Non-Linear Residue Codes for Robust Public-Key Arithmetic,” Proc. Third Workshop Fault Tolerance and Diagnosis in Cryptography (FTDC), pp. 173-184, 2006.
[21] C.W. Chiou, C.Y. Lee, A.W. Deng, and J.M. Lin, “Concurrent Error Detection in Montgomery Multiplication over $GF(2^m)$ ,” IEICE Trans. Fundamentals of Electronics, Comm. and Computer Sciences, vol. E89-A, no. 2, pp. 566-574, 2006.
[22] C.Y. Lee, C.W. Chiou, and J.M. Lin, “Concurrent Error Detection in a Polynomial Basis Multiplier over $GF(2^m)$ ,” J. Electronic Testing, vol. 22, no. 2, pp. 143-150, 2006.
[23] J.H. Patel and L.Y. Fung, “Concurrent Error Detection in ALU's by REcomputing with Shifted Operands,” IEEE Trans. Computers, vol. 31, no. 7, pp. 589-595, July 1982.
[24] J.H. Patel and L.Y. Fung, “Concurrent Error Detection in Multiply and Divide Arrays,” IEEE Trans. Computers, vol. 32, no. 4, pp.417-422, Apr. 1983.
[25] M. Wang and I.F. Blake, “Bit Serial Multiplication in Finite Fields,” SIAM J. Discrete Math., vol. 3, no. 1, pp. 140-148, 1990.
[26] G. Seroussi, “Table of Low-Weight Binary Irreducible Polynomials,” Technical Report HPL-98-135, HP Labs, Aug. 1998.
[27] C.L. Wang and J.L. Lin, “Systolic Array Implementation of Multipliers for Finite Fields $GF(2^m)$ ,” IEEE Trans. Circuits and Systems, vol. 38, no. 7, pp. 796-800, July 1991.
[28] C.S. Yeh, I.S. Reed, and T.K. Truong, “Systolic Multipliers for Finite Fields $GF(2^m)$ ,” IEEE Trans. Computers, vol. 33, no. 4, pp.357-360, Apr. 1984.
[29] C.Y. Lee, Y.H. Chen, C.W. Chiou, and J.M. Lin, “Unified Parallel Systolic Multiplier over $GF(2^m)$ ,” J. Computer Science and Technology, vol. 22, no. 1, pp. 28-38, Jan. 2007.
[30] S. Fenn, M. Benaissa, and O. Taylor, “Dual Basis Systolic Multipliers for $GF(2^m)$ ,” IEE Proc. Computers and Digital Techniques, vol. 144, no. 1, pp. 43-46, Jan. 1997.
[31] C.Y. Lee, C.W. Chiou, and J.M. Lin, “Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of $GF(2^m)$ ,” J.Electronic Testing, vol. 21, no. 5, pp. 539-549, 2005.
[32] A.J. Menezes, I.F. Blake, G.X. Hong, R.C. Mullin, S.A. Vanstone, and T. Yaghoobian, Applications of Finite Fields. Springer-Verlag, 1993.
[33] B. Sunar and C.K. Koc, “An Efficient Optimal Normal Basis TypeII Multiplier,” IEEE Trans. Computers, vol. 50, no. 1, pp. 83-87, Jan. 2001.
[34] S. Kwon, “A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over $GF(2^m)$ Using an Optimal Normal Basis of Type II,” Proc. 16th IEEE Symp. Computer Arithmetic (ARITH-16 '03), 2003.
[35] I. Koren and C. Krishna, Fault-Tolerant Systems. Morgan-Kaufman, 2007.

Index Terms:
Finite-field operations, concurrent error detection (CED), concurrent error correction (CEC), polynomial basis, dual basis, normal basis, pipelined architectures, systolic arrays.
Citation:
Siavash Bayat-Sarmadi, M. Anwar Hasan, "Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures," IEEE Transactions on Computers, vol. 58, no. 11, pp. 1553-1567, Nov. 2009, doi:10.1109/TC.2009.62
Usage of this product signifies your acceptance of the Terms of Use.