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Ghassem Jaberipur, Amir Kaivani, "Improving the Speed of Parallel Decimal Multiplication," IEEE Transactions on Computers, vol. 58, no. 11, pp. 15391552, November, 2009.  
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@article{ 10.1109/TC.2009.110, author = {Ghassem Jaberipur and Amir Kaivani}, title = {Improving the Speed of Parallel Decimal Multiplication}, journal ={IEEE Transactions on Computers}, volume = {58}, number = {11}, issn = {00189340}, year = {2009}, pages = {15391552}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2009.110}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Improving the Speed of Parallel Decimal Multiplication IS  11 SN  00189340 SP1539 EP1552 EPD  15391552 A1  Ghassem Jaberipur, A1  Amir Kaivani, PY  2009 KW  Decimal computer arithmetic KW  parallel decimal multiplication KW  partial product generation and reduction KW  logic design. VL  58 JA  IEEE Transactions on Computers ER   
[1] M.F. Cowlishaw, “Decimal FloatingPoint: Algorism for Computers,” Proc. 16th IEEE Symp. Computer Arithmetic, pp. 104111, June 2003.
[2] F.Y. Busaba, C.A. Krygowski, W.H. Li, E.M. Schwarz, and S.R. Carlough, “The IBM z900 Decimal Arithmetic Unit,” Proc. Asilomar Conf. Signals, Systems, Computers, vol. 2, pp. 13351339, Nov. 2001.
[3] S. Shankland, “IBM's POWER6 Gets Help with Math, Multimedia,” ZDNet News, Oct. 2006.
[4] C.F. Webb, “IBM z10: The NextGeneration Mainframe Microprocessor,” IEEE Micro, vol. 28, no. 2, pp. 1929, Mar./Apr. 2008.
[5] IEEE Standards Committee, 7542008 IEEE Standard for FloatingPoint Arithmetic, (http://ieeexplore.IEEE.org/servlet opac?punumber=4610933 ), pp. 158, Aug. 2008, DOI: 10.1109/IEEESTD.2008.4610935.
[6] M. Schmookler and A. Weinberger, “High Speed Decimal Addition,” IEEE Trans. Computers, vol. 20, no. 8, pp. 862866, Aug. 1971.
[7] J. Thompson, K. Nandini, and M.J. Schulte, “A 64Bit Decimal FloatingPoint Adder,” Proc. IEEE Computer Soc. Ann. Symp. VLSI Emerging Trends VLSI Systems Design (ISVLSI '04), pp. 197198, Feb. 2004.
[8] A. Vazquez and E. Antelo, “Conditional Speculative Decimal Addition,” Proc. Seventh Conf. Real Numbers Computers (RNC 7), pp. 4757, July 2006.
[9] R.D. Kenney and M.J. Schulte, “HighSpeed Multioperand Decimal Adders,” IEEE Trans. Computers, vol. 54, no. 8, pp. 953963, Aug. 2005.
[10] L. Dadda, “Multi Operand Parallel Decimal Adder: A Mixed Binary and BCD Approach,” IEEE Trans. Computers, vol. 56, no. 10, pp. 13201328, Oct. 2007.
[11] M.A. Erle and M.J. Schulte, “Decimal Multiplication via CarrySave Addition,” Proc. Conf. ApplicationSpecific Systems, Architectures, Processors, pp. 348358, June 2003.
[12] R.D. Kenney, M.J. Schulte, and M.A. Erle, “A HighFrequency Decimal Multiplier,” Proc. IEEE Int'l. Conf. Computer Design: VLSI Computers Processors (ICCD), pp. 2629, Oct. 2004.
[13] M.A. Erle, E.M. Schwartz, and M.J. Schulte, “Decimal Multiplication with Efficient Partial Product Generation,” Proc. 17th IEEE Symp. Computer Arithmetic, pp. 2128, June 2005.
[14] W. LiangKai and M.J. Schulte, “Decimal FloatingPoint Division Using NewtonRaphson Iteration,” Proc. 15th Int'l. Conf. ApplicationSpecific Systems, Architectures Processors, pp. 8495, 2004.
[15] H. Nikmehr, B. Phillips, and C.C. Lim, “Fast Decimal FloatingPoint Division,” IEEE Trans. VLSI Systems, vol. 14, no. 9, pp. 951961, Sept. 2006.
[16] T. Lang and A. Nannarelli, “A Radix10 DigitRecurrence Division Unit: Algorithm and Architecture,” IEEE Trans. Computers, vol. 56, no. 6, pp. 727739, June 2007.
[17] L. Wang and M.J. Schulte, “A Decimal FloatingPoint Divider Using NewtonRaphson Iteration,” J. VLSI Signal Processing Systems, vol. 14, no. 1, pp. 318, Oct. 2007.
[18] T. Lang and A. Nannarelli, “A Radix10 Combinational Multiplier,” Proc. Asilomar Conf. Signals, Systems, Computers, pp. 313317, Nov. 2006.
[19] I.D. Castellanos and J.E. Stine, “Compressor Trees for Decimal Partial Product Reduction,” Proc. 18th ACM Great Lakes Symp. VLSI, pp. 107110, May 2008.
[20] A. Vazquez, E. Antelo, and P. Montuschi, “A New Family of HighPerformance Parallel Decimal Multipliers,” Proc. 18th IEEE Symp. Computer Arithmetic, pp. 195204, June 2007.
[21] I.E. Sutherland, R.F. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, 1999.
[22] G. Jaberipur and A. Kaivani, “BinaryCoded Decimal Digit Multipliers,” IET Computers & Digital Techniques, vol. 1, no. 4, pp. 377381, July 2007.
[23] R.K. Richards, Arithmetic Operations in Digital Computers. Van Nostrand, 1955.
[24] R.H. Larson, “High Speed Multiply Using Four Input Carry Save Adder,” IBM Technical Disclosure Bull., vol. 16, no. 7, pp. 20532054, Dec. 1973.
[25] T. Ueda, “Decimal Multiplying Assembly and Multiply Module,” US Patent 5379245, Jan. 1995.
[26] C.S. Wallace, “A Suggestion for Fast Multiplier,” IEEE Trans. Electronic Computers, vol. 13, no. 2, pp. 1417, Feb. 1964.
[27] S.K. Mathew, M. Anders, R.K. Krishnamurthy, and S. Borkar, “A 4Ghz 130 nm Address Generation Unit with 32Bit SparseTree Adder Core,” IEEE J. SolidState Circuits, vol. 38, no. 5, pp. 689695, May 2003.
[28] P.M. Kogge and H.S. Stone, “A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations,” IEEE Trans. Computers, vol. 22, no. 8, pp.786793, Aug. 1973.
[29] B. Hickmann, A. Krioukov, M. Schulte, and M. Erle, “A Parallel IEEE P754 Decimal FloatingPoint Multiplier,” Proc. 25th Int'l. Conf. Computer Design (ICCD '07), pp. 296303, Oct. 2007.
[30] C. Grecu, P.P. Pande, A. Ivanov, and R. Saleh, “Timing Analysis of Network on Chip Architectures for MPSoC Platforms,” Microelectronics J., vol. 36, no. 9, pp. 833845, Sept. 2005.
[31] J.D. Nicoud, “Iterative Arrays for Radix Conversion,” IEEE Trans. Computers, vol. 20, no. 12, pp. 14791489, Dec. 1971.