Publication 2009 Issue No. 10 - October Abstract - Correcting the Normalization Shift of Redundant Binary Representations
Correcting the Normalization Shift of Redundant Binary Representations
October 2009 (vol. 58 no. 10)
pp. 1435-1439
 ASCII Text x Peter Kornerup, "Correcting the Normalization Shift of Redundant Binary Representations," IEEE Transactions on Computers, vol. 58, no. 10, pp. 1435-1439, October, 2009.
 BibTex x @article{ 10.1109/TC.2009.38,author = {Peter Kornerup},title = {Correcting the Normalization Shift of Redundant Binary Representations},journal ={IEEE Transactions on Computers},volume = {58},number = {10},issn = {0018-9340},year = {2009},pages = {1435-1439},doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2009.38},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on ComputersTI - Correcting the Normalization Shift of Redundant Binary RepresentationsIS - 10SN - 0018-9340SP1435EP1439EPD - 1435-1439A1 - Peter Kornerup, PY - 2009KW - Floating-point additionKW - normalizationKW - leading-one determination (LOD)KW - leading-zero anticipation (LZA).VL - 58JA - IEEE Transactions on ComputersER -
Peter Kornerup, University of Southern Denmark, Odense
An important problem in the realization of floating-point subtraction is the identification of the position of the first nonzero digit in a radix-represented number, since the significand usually is to be represented left-normalized in the part of the word(s) allocated for representing its value. There are well-known log-time algorithms for determining this position for numbers in nonredundant representations, which may also be applied to suitably (linear-time) transformed redundant representations. However, due to the redundancy in the latter case, the position thus determined may need a correction by one. When determination of the shift amount is to be performed in parallel with conversion to nonredundant representation (the subtraction), it must be performed on the redundant representation. This is also the case when the significand is to be retained in a redundant representation until the final rounding. This paper presents an improved algorithm for determining the need for a correction of the normalization shift amount, which can be run in parallel with the algorithm finding the “approximate” position.

[1] F. Arakawa, T. Hayashi, and M. Nishibori, “An Exact Leading Non-Zero Detector for a Floating Point Unit,” IEICE Trans. Electronics, vol. E88-C, no. 4, pp. 570-575, 2005.
[2] J.D. Bruguera and T. Lang, “Leading-One Prediction with Concurrent Position Correction,” IEEE Trans. Computers, vol. 48, no. 10, pp. 1083-1097, Oct. 1999.
[3] M. Daumas and D.W. Matula, “Further Reducing the Redundancy of Notation over a Minimally Redundant Digit Set,” J. VLSI Signal Processing, vol. 33, nos. 1/2, pp. 7-18, 2003.
[4] C.N. Hinds and D.R. Lutz, “A Small and Fast Leading One Predictor Corrector Circuit,” Proc. 39th Asilomar Conf. Signals, Systems and Computers, pp. 1181-1185, 2005.
[5] E. Hokenek and R.K. Montoye, “Leading-Zero Anticipator (LZA) in the IBM RISC System/6000 Floating Point Execution Unit,” IBM J. Research and Development, vol. 34, no. 1, pp. 71-77, 1990.
[6] N. Ohkubo, M. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, “A 4.4 ns CMOS 54 $\times$ 54-b Multiplier Using Pass Transistor Multiplexer,” IEEE J. Solid State Circuits, vol. 30, no. 3, pp. 251-257, Mar. 1995.
[7] V.G. Oklobdzij, “An Algorithm and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis,” IEEE Trans. Very Large Scale Integration Systems, vol. 2, no. 1, pp. 124-128, Mar. 1999.
[8] M. Olivieri, F. Pappalardo, S. Smorfa, and G. Visalli, “Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units,” IEEE Trans. Circuits and Systems II, Express Briefs, vol. 54, no. 8, pp. 685-689, Aug. 2007.
[9] M.S. Schmookler and K.I. Nowka, “Leading Zero Anticipation and Detection—A Comparison of Methods,” Proc. 15th IEEE Symp. Computer Arithmetic, pp. 7-12, 2001.
[10] G. Zhang, W.-W. Hu, and Z.-C. Qi, “Parallel Error Detection for Leading Zero Anticipation,” J. Computer Science & Technolology, vol. 21, no. 6, pp.901-906, 2006.

Index Terms: