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Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers
October 2009 (vol. 58 no. 10)
pp. 1346-1355
Jin-Hao Tu, National Chiao Tung University, Hsinchu
Lan-Da Van, National Chiao Tung University, Hsinchu
In this paper, we propose a pipelined reconfigurable fixed-width Baugh-Wooley multiplier design framework that provides four configuration modes (CMs): n \times n fixed-width multiplier, two n/2 \times n/2 fixed-width multipliers, n/2 \times n/2 full-precision multiplier, and two n/4 \times n/4 full-precision multipliers. Furthermore, low-power schemes including gated clock and zero input techniques are employed to achieve the power-efficient pipelined reconfigurable design. The presented power-efficient pipelined reconfigurable fixed-width multiplier design not only generates a family of widely used multipliers but also leads to 10.59, 21.7, 28.84, and 31.58 percent power saving, on average, for n = 8, 16, 24, and 32, respectively, compared with that of the pipelined reconfigurable fixed-width multiplier without using the low-power schemes. On the other hand, compared with non-reconfigurable pipelined multiplier, we can save 0.81, 12.46, 17.93, and 23.2 percent power consumption, respectively, for n = 8, 16, 24, and 32.

[1] C.R. Baugh and B.A. Wooley, “A Two's Complement Parallel Array Multiplication Algorithm,” IEEE Trans. Computers, vol. 22, no. 12, pp. 1045-1047, Dec. 1973.
[2] A.D. Booth, “A Signed Binary Multiplication Techniques,” Quarterly J. Mechanics and Applied Math., vol. 4, pp. 236-240, 1951.
[3] O.L. MacSorley, “High-Speed Arithmetic in Binary Computer,” Proc. Conf. Institute of Radio Engineers (IRE '61), vol. 49, pp. 67-91, 1961.
[4] K. Hwang, Computer Arithmetic: Principles, Architecture, and Design. John-Wiley, 1979.
[5] F. Cavanagh, Digital Computer Arithmetic: Design and Implementation. McGraw-Hill, 1984.
[6] M.D. Ercegovac and T. Lang, Digital Arithmetic. Morgan and Kaufmann, 2004.
[7] S.L. Freeny, “Special-Purpose Hardware for Digital Filtering,” Proc. IEEE, vol. 63, no. 4, pp. 633-647, Apr. 1975.
[8] Y.C. Lim, “Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications,” IEEE Trans. Computers, vol. 41, no. 10, pp. 1333-1336, Oct. 1992.
[9] M.J. Schulte and E.E. SwartzlanderJr., “Truncated Multiplication with Correction Constant,” Proc. Workshop Very Large Scale Integration (VLSI) Systems Signal Processing, VI, pp. 388-396, 1993.
[10] S.S. Kidambi, F. El-Guibaly, and A. Antoniou, “Area-Efficient Multipliers for Digital Signal Processing Applications,” IEEE Trans. Circuits and Systems, vol. 43, no. 2, pp. 90-94, Feb. 1996.
[11] E.J. King and E.E. SwartzlanderJr., “Data-Dependent Truncation Scheme for Parallel Multipliers,” Proc. 31st Asilomar Conf. Signals, Systems, and Computers, vol. 2, pp. 1178-1182, 1997.
[12] E.E. SwartzlanderJr., “Truncated Multiplication with Approximate Rounding,” Proc. 33rd Asilomar Conf. Signals, Systems, and Computers, vol. 2, pp. 1480-1483, 1999.
[13] J.M. Jou, S.R. Kuang, and R.D. Chen, “Design of Low-Error Fixed-Width Multiplier for DSP Applications,” IEEE Trans. Circuits and Systems, vol. 46, no. 6, pp. 836-842, June 1999.
[14] L.D. Van, S.S. Wang, and W.S. Feng, “Design of the Lower-Error Fixed-Width Multiplier and Its Application,” IEEE Trans. Circuits and Systems, vol. 47, no. 10, pp. 1112-1118, Oct. 2000.
[15] K.J. Cho, K.C. Lee, J.G. Chung, and K.K. Parhi, “Design Low-Error Fixed-Width Modified Booth Multiplier,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5, pp.522-531, May 2004.
[16] L.D. Van and C.C. Yang, “Generalized Low-Error Area-Efficient Fixed-Width Multipliers,” IEEE Trans. Circuits and Systems I, vol. 52, no. 8, pp. 1608-1619, Aug. 2005.
[17] S. Krithivasan and M.J. Schulte, “Multiplier Architectures for Media Processing,” Proc. IEEE Asilomar Conf. Signals, Systems, and Computers, vol. 2, pp. 2193-2197, Nov. 2003.
[18] Y.-H. Huang, H.-P. Ma, M.-L. Liou, and T.-D. Chiueh, “A 1.1 G MAC/s Subword-Parallel Digital Signal Processor for Wireless Communication Applications,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 169-183, Jan. 2004.
[19] S. Krithivasan, M.J. Schulte, and J. Glossner, “A Subword-Parallel Multiplication and Sum-of-Squares Unit,” Proc. IEEE CS Ann. Symp. Very Large Scale Integration (VLSI) Systems, pp.273-274, Feb. 2004.
[20] Y.-L. Tsao, W.-H. Chen, M.-H. Tan, M.-C. Lin, and S.-J. Jou, “Low-Power Embedded DSP Core for Communication Systems,” EURASIP J. Applied Signal Processing, pp. 1355-1370, Jan. 2003.
[21] D. Tan, A. Danysh, and M. Liebelt, “Multiple-Precision Fixed-Point Vector Multiply-Accumulator Using Shared Segmentation,” Proc. IEEE Symp. Computer Arithmetic, pp. 12-19, June 2003.
[22] C.L. Wey and J.F. Li, “Design of Reconfigurable Array Multipliers and Multiplier-Accumulators,” Proc. IEEE Asia-Pacific Conf. Circuits and Systems, pp. 37-40, Dec. 2004.
[23] R. Lin, “Reconfigurable Parallel Inner Product Processor Architecture,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 9, no. 2, pp. 261-272, Apr. 2001.
[24] K. Tatas, G. Koutroumpezis, D. Soudris, and A. Thanailakis, “Architecture Design of a Coarse-Grain Reconfigurable Multiply-Accumulate Unit for Data-Intensive Applications,” Integration, the VLSI J., vol. 40, pp. 74-93, Feb. 2007.
[25] S.D. Haynes and P.Y.K. Cheung, “Configurable Multiplier Blocks for Embedding in FPGAs,” Electronics Letter, vol. 34, no. 7, pp. 638-639, Apr. 1998.
[26] J. Di and J.S. Yuan, “Run-Time Reconfigurable Power-Aware Pipelined Signed Array Multiplier Design,” Proc. IEEE Int'l Symp. Signals, Circuits, and Systems, vol. 2, pp. 405-406, July 2003.
[27] M. Sjalander, M. Drazdziulis, P. Larsson-Edefors, and H. Eriksson, “A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating,” Proc. IEEE Int'l Symp. Circuits, and Systems, vol. 2, pp. 1654-1657, May 2005.
[28] S.-R. Kuang and J.-P. Wang, “Design of Power-Efficient Pipelined Truncated Multipliers with Various Output Precision,” IET Computers & Digital Techniques, vol. 1, pp. 129-136, Mar. 2007.

Index Terms:
Baugh-Wooley algorithm, full-precision multiplier, fixed-width multiplier, pipeline, power efficient, and reconfigurable.
Jin-Hao Tu, Lan-Da Van, "Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers," IEEE Transactions on Computers, vol. 58, no. 10, pp. 1346-1355, Oct. 2009, doi:10.1109/TC.2009.89
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