Subscribe
Issue No.10 - October (2009 vol.58)
pp: 1332-1345
Arash Hariri , University of Western Ontario, London
Arash Reyhani-Masoleh , University of Western Ontario, London
ABSTRACT
Multiplication and squaring are main finite field operations in cryptographic computations and designing efficient multipliers and squarers affect the performance of cryptosystems. In this paper, we consider the Montgomery multiplication in the binary extension fields and study different structures of bit-serial and bit-parallel multipliers. For each of these structures, we study the role of the Montgomery factor, and then by using appropriate factors, propose new architectures. Specifically, we propose two bit-serial multipliers for general irreducible polynomials, and then derive bit-parallel Montgomery multipliers for two important classes of irreducible polynomials. In this regard, first we consider trinomials and provide a way for finding efficient Montgomery factors which results in a low time complexity. Then, we consider type-II irreducible pentanomials and design two bit-parallel multipliers which are comparable to the best finite field multipliers reported in the literature. Moreover, we consider squaring using this family of irreducible polynomials and show that this operation can be performed very fast with the time complexity of two XOR gates.
INDEX TERMS
Montgomery multiplication, squaring, finite (or Galois) fields, bit-serial, bit-parallel, trinomials, pentanomials.
CITATION
Arash Hariri, Arash Reyhani-Masoleh, "Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over GF(2^m)", IEEE Transactions on Computers, vol.58, no. 10, pp. 1332-1345, October 2009, doi:10.1109/TC.2009.70
REFERENCES
 [1] E.D. Mastrovito , “VLSI Architectures for Computation in Galois Fields,” PhD dissertation, Linkoping Univ., 1991. [2] L. Song and K. Parhi , “Low-Energy Digit-Serial/Parallel Finite Field Multipliers,” J. Very Large Scale Integration (VLSI) Signal Processing, vol. 19, no. 2, pp. 149-166, 1998. [3] A. Reyhani-Masoleh and M. Hasan , “Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over $GF (2^m)$ ,” IEEE Trans. Computers, vol. 53, no. 8, pp. 945-959, Aug. 2004. [4] F. Rodriguez-Henriguez and C. Koc , “Parallel Multipliers Based on Special Irreducible Pentanomials,” IEEE Trans. Computers, vol. 52, no. 12, pp. 1535-1542, Dec. 2003. [5] C. Koc and T. Acar , “Montgomery Multiplication in $GF(2^k)$ ,” Designs, Codes and Cryptography, vol. 14, no. 1, pp. 57-69, 1998. [6] H. Fan and M. Hasan , “Fast Bit Parallel Shifted Polynomial Basis Multipliers in $GF (2^n)$ ,” IEEE Trans. Circuits and Systems I, Fundamental Theory and Applications, vol. 53, no. 12, pp. 2606-2615, Dec. 2006. [7] P. Montgomery , “Modular Multiplication without Trial Division,” Math. Computation, vol. 44, no. 170, pp. 519-521, 1985. [8] K. Sakiyama , L. Batina , B. Preneel , and I. Verbauwhede , “High-Performance Public-Key Cryptoprocessor for Wireless Mobile Applications,” Mobile Networks and Applications, vol. 12, no. 4, pp.245-258, 2007. [9] N. Mentens , S.B. Ors , B. Preneel , and J. Vandewalle , “An FPGA Implementation of a Montgomery Multiplier over $GF(2^m)$ ,” Proc. Seventh IEEE Workshop Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 121-128, 2004. [10] C. Chiou , C. Lee , A. Deng , and J. Lin , “Concurrent Error Detection in Montgomery Multiplication over $GF (2^m)$ ,” IEICE Trans. Fundamentals of Electronics, Comm. and Computer Sciences, vol. 89, no. 2, pp. 566-574, 2006. [11] L. Batina , N. Mentens , B. Preneel , and I. Verbauwhede , “Balanced Point Operations for Side Channel Protection of Elliptic Curve Cryptography,” Proc. IEE: Information Security, vol. 152, no. 1, pp.57-65, 2005. [12] E. Savas , A. Tenca , M. Ciftcibasi , and Ç. Koc , “Novel Multiplier Architectures for $GF (p)$ and $GF (2^n)$ ,” Proc. IEE: Computers and Digital Techniques, vol. 151, no. 2, pp. 147-160, 2004. [13] D. Harris , R. Krishnamurthy , M. Anders , S. Mathew , and S. Hsu , “An Improved Unified Scalable Radix-2 Montgomery Multiplier,” Proc. 17th IEEE Symp. Computer Arithmetic, pp. 172-178, 2005. [14] A. Fournaris and O. Koufopavlou , “Versatile Multiplier Architectures in $GF(2^k)$ Fields Using the Montgomery Multiplication Algorithm,” Integration, the Very Large Scale Integration (VLSI) J., vol. 41, no. 3, pp. 371-384, 2008. [15] J.S. Horng and E.H. Lu , “Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF( $2^m$ ),” IEEE Trans. Computers, vol. 54, no. 9, pp. 1061-1070, Sept. 2005. [16] H. Wu , “Montgomery Multiplier and Squarer for a Class of Finite Fields,” IEEE Trans. Computers, vol. 51, no. 5, pp. 521-529, May 2002. [17] B. Ansari and M. Hasan , “High Performance Architecture of Elliptic Curve Scalar Multiplication,” IEEE Trans. Computers, vol. 57, no. 11, pp. 1443-1453, Nov. 2008. [18] Y. Lee , K. Sakiyama , L. Batina , and I. Verbauwhede , “Elliptic-Curve-Based Security Processor for RFID,” IEEE Trans. Computers, vol. 57, no. 11, pp. 1514-1527, Nov. 2008. [19] K. Sakiyama , L. Batina , B. Preneel , and I. Verbauwhede , “Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over $GF(2^n)$ ,” IEEE Trans. Computers, vol. 56, no. 9, pp. 1269-1282, Sept. 2007. [20] Recommended Elliptic Curves for Federal Government Use, csrc. nist.gov/groups/ST/toolkit/documents/ dssNISTReCur.pdf, 2009. [21] T. Beth and D. Gollman , “Algorithm Engineering for Public Key Algorithms,” IEEE J. Selected Areas in Comm., vol. 7, no. 4, pp. 458-466, May 1989. [22] S. Kumar , T. Wollinger , and C. Paar , “Optimum Digit Serial $GF(2^m$ ) Multipliers for Curve-Based Cryptography,” IEEE Trans. Computers, vol. 55, no. 10, pp. 1306-1311, Oct. 2006. [23] J. Imana and J. Sanchez , “Bit-Parallel Finite Field Multipliers for Irreducible Trinomials,” IEEE Trans. Computers, vol. 55, no. 5, pp.520-533, May 2006. [24] R. Lidl and H. Niederreiter , Introduction to Finite Fields and Their Applications. Cambridge Univ. Press, 1986. [25] S. Park , K. Chang , and D. Hong , “Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis,” IEEE Trans. Computers, vol. 55, no. 9, pp. 1211-1215, Sept. 2006. [26] J. Imana , R. Hermida , and F. Tirado , “Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 14, no. 12, pp. 1388-1393, Dec. 2006. [27] H. Wu , “Low Complexity Bit-Parallel Finite Field Arithmetic Using Polynomial Basis,” Proc. First Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES), pp. 280-291, 1999. [28] J. Guajardo , T. Güneysu , S. Kumar , C. Paar , and J. Pelzl , “Efficient Hardware Implementation of Finite Fields with Applications to Cryptography,” Acta Applicandae Math.: Int'l Survey J. Applying Math. and Math. Applications, vol. 93, no. 1, pp. 75-118, 2006.