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Tunable and Energy Efficient Bus Encoding Techniques
August 2009 (vol. 58 no. 8)
pp. 1049-1062
Dinesh C. Suresh, Advanced Micro Devices, Santa Clara
Banit Agrawal, University of California Santa Barbara, Santa Barbara
Jun Yang, University of Pittsburg, Pittsburg
Walid A. Najjar, University of California Riverside, Riverside
Off-Chip buses constitute a significant portion of the total system power in embedded systems. Many research works have focused on reducing power consumption in the off-chip buses. While numerous techniques exist for reducing bus power in address buses, only a handful of techniques have been proposed for off-chip data bus power reduction. In this paper, we propose two novel data bus encoding schemes to reduce power consumption in the data buses. The first scheme called Variable Length Value Encoder (VALVE) is capable of detecting and encoding variable lengths of repeated bit patterns in the data. The second technique called Tunable Bus Encoder (TUBE) encodes repetition in contiguous as well as noncontiguous bit positions of data values. Both schemes require just one external control signal to encode data values. TUBE is the first proposed hardware-based bus encoding scheme capable of detecting and encoding both contiguous and noncontiguous bit patterns of varying widths. Experimental evaluation on a large set of benchmarks shows an energy reduction of 58 percent and 60 percent on average for VALVE and TUBE, respectively. We evaluate the performance penalty incurred due to the codec delay and it is found to be 0.45 percent of the total program execution time. We also quantify our hardware overhead in terms of area, delay, and energy consumption. In 0.18 \mu m technology, VALVE and TUBE require a modest area of 0.0486 mm^2 and 0.0521 mm^2, respectively.

[1] sramlowpower-4m.html, 2009.
[2] Y. Aghaghiri, F. Fallah, and M. Pedram, “Irredundant Address Bus Encoding for Low Power,” Proc. 2001 Int'l Symp. Low Power Electronics and Design (ISLPED '01), pp. 182-187, 2001.
[3] K. Basu, A. Choudhary, J. Pisharath, and M. Kandemir, “Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses,” Proc. 35th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-35), 2002.
[4] L. Benini, G. De Micheli, E. Macci, D. Scuito, and C. Silvano, “Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Bases Systems,” Proc. ACM Great Lakes Symp. VLSI (GSVLSI '97), pp. 77-82, 1997.
[5] T.D. Burd and R.W. Brodersen, “Design Issues for Dynamic Voltage Scaling,” Proc. 2000 Int'l Symp. Low Power Electronics and Design (ISLPED '00), pp. 9-14, 2000.
[6] D. Burger and T. Austin, “The SimpleScalar Tool Set, Version 2.0,” technical report, Computer Science Dept., Univ. of Wisconsin-Madison, 1997.
[7] F. Catthoor, S. Wuytack, E. De Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle, Exploration of Memory Organization for Embedded Multimedia System Design. Kluwer Academic Publishers, 1998.
[8] N. Chang, K. Kim, and J. Cho, “Bus Encoding for Low-Power High-Performance Memory Systems,” Proc. Design Automation Conf., pp. 800-805, Aug. 2000.
[9] D. Citron and L. Rudolph, “Creating a Wider Bus Using Caching Techniques,” Proc. First Int'l Symp. High Performance Computer Architecture (HPCA '95), pp. 90-99, 1995.
[10] L. Deng and M.D.F. Wong, “Energy Optimization in Memory Address Bus Structure for Application-Specific Systems,” Proc. 15th ACM Great Lakes Symp. VLSI (GSVLSI '05), pp. 232-237, 2005.
[11] H. Deogun, R. Rao, D. Sylvester, and D. Blaauw, “Leakage- and Crosstalk-Aware Bus Encoding for Total Power Reduction,” Proc. IEEE/ACM Design Automation Conf. (DAC '04), pp. 779-782, June 2004.
[12] M. Farrens and A. Park, “Dynamic Base Register Caching: A Technique for Reducing Address Bus Width,” Proc. 18th Int'l Symp. Computer Architecture (ISCA), pp. 128-137, May 1991.
[13] I.Y.L. Hsiao, D.H. Wang, and C.W. Jen, “Power Modeling and Low-Power Design of Content Addressable Memories,” Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '01), vol. 4, pp. 926-929, May 2001.
[14] H. Kaul, D. Sylvester, D. Blaauw, T. Austin, and T. Mudge, “DVS for On-Chip Bus Designs Based on Timing Error Correction,” Proc. ACM/IEEE Design, Automation, and Test Europe (DATE '05) Conf., pp. 80-85, Mar. 2005.
[15] C. Lee, M. Potkonjak, and W. Mangione-Smith, “MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems,” Proc. Int'l Symp. Microarchitecture (MICRO-30), pp. 330-335, 1997.
[16] T. Lv, J. Henkel, H. Lekatsas, and W. Wolf, “An Adaptive Dictionary Encoding Scheme for SOC Data Buses,” Proc. Design Automation and Test in Europe (DATE '02) Conf., pp. 1059-1064, 2002.
[17] F. Pappalardo , M. Olivieri, and G. Visalli, “Design Issues for Bus Switch Systems in Deep Sub-Micro Metric CMOS Technologies,” Proc. IASTED Conf. Circuits, Signals, and Systems (CSS '05), Nov. 2005.
[18] M. Mamidipaka, D. Hirschberg, and N. Dutt, “Low Power Address Bus Encoding Using Self-Organizing Lists,” Proc. Int'l Symp. Low Power Electronics and Design (ISLPED '01), pp. 188-193, Aug. 2001.
[19] G. Memik, W.H.M. Smith, and W. Hu, “NetBench: A Benchmarking Suite for Network Processors,” Proc. Int'l Conf. Computer Aided Design (ICCAD '01), pp. 39-42, 2001.
[20] E. Musoll, T. Lang, and J. Cortadella, “Working Zone Encoding for Reducing the Energy in Microprocessor Address Buses,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 6, no. 4, pp.568-572, Dec. 1998.
[21] P. Petrov and A. Orailoglu, “Low-Power Instruction Bus Encoding for Embedded Processors,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, pp. 812-826, Aug. 2004.
[22] A. Raghunathan, N.K. Jha, and S. Dey, High-Level Power Analysis and Optimization. Kluwer Academic Publishers, 1998.
[23] Y. Shin and K. Choi, “Narrow Bus Encoding for Low Power Systems,” Proc. 2000 Conf. Asia South Pacific Design Automation (ASP-DAC '00), pp. 217-220, 2000.
[24] P. Shivakumar and N.P. Jouppi, “Cacti 3.0: An Integrated Cache Timing, Power and Area Model,” technical report, Western Research Lab (WRL) Research Report, 2001.
[25] P. Shivakumar and N.P. Jouppi, “Cacti 5.0,” technical report, 2007.
[26] SPECINT2000, http://www.specbench.orgcpu2000, 2000.
[27] M. Stan and W. Burleson, “Coding a Terminated Bus for Low Power,” Proc. Fifth Great Lakes Symp. VLSI, Mar. 1995.
[28] M.R. Stan and W.P. Burleson, “Bus-Invert Coding for Low Power I/O,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 3, no. 1, pp. 49-58, Mar. 1995.
[29] C.L. Su, C.Y. Tsui, and A.M. Despain, “Saving Power in the Control Path of Embedded Processors,” IEEE Design and Test of Computers, vol. 11, no. 4, pp. 24-30, Oct.-Dec. 1994.
[30] D.C. Suresh, B. Agrawal, J. Yang, W. Najjar, and L. Bhuyan, “Power Efficient Encoding Techniques for Off-Chip Data Buses,” Proc. Int'l Conf. Compilers Architecture and Synthesis for Embedded Systems (CASES '03), 2003.
[31] D.C. Suresh, J. Yang, C. Zhang, B. Agrawal, and W. Najjar, “FV-MSB: A Scheme for Reducing Transition Activity on Data Buses,” Proc. Int'l Conf. High Performance Computing (HiPC '03), 2003.
[32] D.C. Suresh, B. Agrawal, W.A. Najjar, and J. Yang, “VALVE: Variable Length Value Encoder for Off-Chip Data Buses,” Proc. 23rd IEEE Int'l Conf. Computer Design (ICCD '05), pp. 631-633, Oct. 2005.
[33] D.C. Suresh, B. Agrawal, J. Yang, and W. Najjar, “A Tunable Bus Encoder for Off-Chip Data Buses,” Proc. 2005 Int'l Symp. Low Power Electronics and Design (ISLPED '05), pp. 319-322, 2005.
[34] V. Wen, M. Whitney, Y. Patel, and J.D. Kubiatowicz, “Exploiting Prediction to Reduce Power on Buses,” Proc. 10th Int'l Symp. High Performance Computer Architecture (HPCA '04), pp. 2-13, 2004.
[35] S. Wong and C. Tsui, “Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus,” Proc. Conf. Design, Automation and Test in Europe (DATE '04), pp. 130-135, 2004.
[36] J. Yang and R. Gupta, “FV-Encoding for Low Power Data I/O,” Proc. ACM/IEEE Int'l Symp. Low Power Electronic Design (ISLPED '01), pp. 84-87, Aug. 2001.
[37] J. Yang, R. Gupta, and C. Zhang, “Frequent Value Encoding for Low Power Data Buses,” ACM Trans. Design and Automation of Electronic Systems, vol. 9, no. 3, pp. 354-384, 2004.

Index Terms:
VALVE, TUBE, power, data buses, encoding, bus switching, hardware design, internal capacitances.
Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, "Tunable and Energy Efficient Bus Encoding Techniques," IEEE Transactions on Computers, vol. 58, no. 8, pp. 1049-1062, Aug. 2009, doi:10.1109/TC.2009.39
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