Publication 2009 Issue No. 7 - July Abstract - Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials
Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials
July 2009 (vol. 58 no. 7)
pp. 1001-1008
 ASCII Text x Alessandro Cilardo, "Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials," IEEE Transactions on Computers, vol. 58, no. 7, pp. 1001-1008, July, 2009.
 BibTex x @article{ 10.1109/TC.2009.16,author = {Alessandro Cilardo},title = {Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials},journal ={IEEE Transactions on Computers},volume = {58},number = {7},issn = {0018-9340},year = {2009},pages = {1001-1008},doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2009.16},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on ComputersTI - Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible PentanomialsIS - 7SN - 0018-9340SP1001EP1008EPD - 1001-1008A1 - Alessandro Cilardo, PY - 2009KW - GF(2^m) bit-parallel multiplicationKW - shifted polynomial basesKW - irreducible pentanomials.VL - 58JA - IEEE Transactions on ComputersER -
Alessandro Cilardo, University of Naples Federico II, Napoli
This work studies efficient bit-parallel multiplication in GF(2^m) for irreducible pentanomials, based on the so-called Shifted Polynomial Bases (SPBs). We derive a closed expression of the reduced SPB product for a class of polynomials x^m+x^{k_s}+ x^{k_{s-1}}+\cdots +x^{k_1}+1, with k_s-k_1\le {m+1\over 2}. Then, we apply the above formulation to the case of pentanomials. The resulting multiplier outperforms, or is as efficient as the best proposals in the technical literature, but it is suitable for a much larger class of pentanomials than those studied so far. Unlike previous works, this property enables the choice of pentanomials optimizing different field operations (for example, inversion), yet preserving an optimal implementation of field multiplication, as discussed and quantitatively proved in the last part of the paper.

[1] I.F. Blake, G. Seroussi, and N.P. Smart, Elliptic Curves in Cryptography. Cambridge Univ. Press, 1999.
[1] I.F. Blake, G. Seroussi, and N.P. Smart, Elliptic Curves in Cryptography. Cambridge Univ. Press, 1999.
[2] H. Fan and Y. Dai, “Fast Bit Parallel $GF(2^m)$ Multiplier for All Trinomials,” IEEE Trans. Computers, vol. 54, no. 4, pp.485-490, Apr. 2005.
[2] H. Fan and Y. Dai, “Fast Bit Parallel $GF(2^m)$ Multiplier for All Trinomials,” IEEE Trans. Computers, vol. 54, no. 4, pp.485-490, Apr. 2005.
[3] H. Fan and M.A. Hasan, “Fast Bit Parallel Shifted Polynomial Basis Multipliers in $GF(2^n)$ ,” IEEE Trans. Circuits and Systems-I, vol. 53, no. 12, pp.2606-2614, Dec. 2006.
[3] H. Fan and M.A. Hasan, “Fast Bit Parallel Shifted Polynomial Basis Multipliers in $GF(2^n)$ ,” IEEE Trans. Circuits and Systems-I, vol. 53, no. 12, pp.2606-2614, Dec. 2006.
[4] K. Fong, D. Hankerson, J. López, and A. Menezes, “Field Inversion and Point Halving Revisited,” IEEE Trans. Computers, vol. 53, no. 8, pp.1047-1059, Aug.. 2004.
[4] K. Fong, D. Hankerson, J. López, and A. Menezes, “Field Inversion and Point Halving Revisited,” IEEE Trans. Computers, vol. 53, no. 8, pp.1047-1059, Aug.. 2004.
[5] J.L. Imaña, R. Hermida, and F. Tirado, “Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials,” IEEE Trans. Very Large Scale Integration (VLSI) Sytems, vol. 14, no. 12, Dec. 2006.
[5] J.L. Imaña, R. Hermida, and F. Tirado, “Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials,” IEEE Trans. Very Large Scale Integration (VLSI) Sytems, vol. 14, no. 12, Dec. 2006.
[6] R. Lidl and H. Niederreiter, Finite Fields (Encyclopedia of Math. and Its Applications), second ed. Cambridge Univ. Press, 1997.
[6] R. Lidl and H. Niederreiter, Finite Fields (Encyclopedia of Math. and Its Applications), second ed. Cambridge Univ. Press, 1997.
[7] Fed. Information Processing Standards Publication 186-2, Digital Signature Standard (DSS), Nat'l Inst. of Standards and Technology (NIST), Feb. 2000.
[7] Fed. Information Processing Standards Publication 186-2, Digital Signature Standard (DSS), Nat'l Inst. of Standards and Technology (NIST), Feb. 2000.
[8] NTL: A Library for Doing Number Theory, http://www.shoup. netntl, 2009.
[8] NTL: A Library for Doing Number Theory, http://www.shoup. netntl, 2009.
[9] S.M. Park, K.Y. Chang, and D. Hong, “Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis,” IEEE Trans. Computers, vol. 55, no. 9, pp.1211-1215, Sept. 2006.
[9] S.M. Park, K.Y. Chang, and D. Hong, “Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis,” IEEE Trans. Computers, vol. 55, no. 9, pp.1211-1215, Sept. 2006.
[10] A. Reyhani-Masoleh and M.A. Hasan, “Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over $GF(2^m)$ ,” IEEE Trans. Computers, vol. 53, no. 8, pp.945-959, Aug. 2004.
[10] A. Reyhani-Masoleh and M.A. Hasan, “Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over $GF(2^m)$ ,” IEEE Trans. Computers, vol. 53, no. 8, pp.945-959, Aug. 2004.
[11] F. Rodriguez-Henriquez and Ç.K. Koç, “Parallel Multipliers Based on Special Irreducible Pentanomials,” IEEE Trans. Computers, vol. 52, no. 12, pp.1535-1542, Dec. 2003.
[11] F. Rodriguez-Henriquez and Ç.K. Koç, “Parallel Multipliers Based on Special Irreducible Pentanomials,” IEEE Trans. Computers, vol. 52, no. 12, pp.1535-1542, Dec. 2003.
[12] E. Savaş, M. Naseer, A.A.-A. Gutub, and Ç.K. Koç, “Efficient Unified Montgomery Inversion with Multibit Shifting,” IEE Proc. Computers and Digital Techniques, vol. 152, no. 4, pp.489-498, July 2005.
[12] E. Savaş, M. Naseer, A.A.-A. Gutub, and Ç.K. Koç, “Efficient Unified Montgomery Inversion with Multibit Shifting,” IEE Proc. Computers and Digital Techniques, vol. 152, no. 4, pp.489-498, July 2005.
[13] G. Seroussi, “Table of Low-Weight Binary Irreducible Polynomials,” Technical Report HPL-98-135, Hewlett-Packard Laboratories, Palo Alto, Calif., http://www.hpl.hp.comtechreports/, Aug. 1998.
[13] G. Seroussi, “Table of Low-Weight Binary Irreducible Polynomials,” Technical Report HPL-98-135, Hewlett-Packard Laboratories, Palo Alto, Calif., http://www.hpl.hp.comtechreports/, Aug. 1998.
[14] T. Zhang and K.K. Parhi, “Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials,” IEEE Trans. Computers, vol. 50, no. 7, pp.734-749, July 2001.
[14] T. Zhang and K.K. Parhi, “Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials,” IEEE Trans. Computers, vol. 50, no. 7, pp.734-749, July 2001.

Index Terms:
GF(2^m) bit-parallel multiplication, shifted polynomial bases, irreducible pentanomials.
Citation:
Alessandro Cilardo, "Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials," IEEE Transactions on Computers, vol. 58, no. 7, pp. 1001-1008, July 2009, doi:10.1109/TC.2009.16