Issue No.07 - July (2009 vol.58)
Akashi Satoh , National Institute of Advanced Industrial Science and Technology, Tokyo
Takeshi Sugawara , Tohoku University, Sendai
Takafumi Aoki , Tohoku University, Sendai
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2008.217
Various high-performance hardware architectures for Galois Counter Mode (GCM) in conjunction with various Advanced Encryption Standard (AES) circuits and multiplier-adders are proposed. A total of 17 GCM-AES circuits were synthesized by using a 130-nm CMOS standard cell library, and the trade-offs between speed and hardware resources were evaluated. Our flexible architectures achieved a wide variety of performances from compact (2.56 Gbps with 34.5 Kgates) to high speed (62.6 Gbps with 979.3 Kgates). All of our architectures support key sizes of 128, 192, and 256 bits, while only one previous approach does. Even with variable-length key support, our architecture also achieved the highest hardware efficiency (defined as throughput per gate) among the designs using the same generation of process technology.
AES, ASIC, high-speed hardware, GCM, multiplier, S-box, VLSI.
Akashi Satoh, Takeshi Sugawara, Takafumi Aoki, "High-Performance Hardware Architectures for Galois Counter Mode", IEEE Transactions on Computers, vol.58, no. 7, pp. 917-930, July 2009, doi:10.1109/TC.2008.217