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Issue No.07 - July (2009 vol.58)

pp: 902-916

Mark A. Erle , IBM and Lehigh University, Macungie

Brian J. Hickmann , University of Wisconsin - Madison, Madison

Michael J. Schulte , University of Wisconsin - Madison, Madison

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2008.218

ABSTRACT

Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents the design of two decimal floating-point multipliers: one whose partial product accumulation strategy employs decimal carry-save addition and one that employs binary carry-save addition. The multiplier based on decimal carry-save addition favors a nonpipelined iterative implementation. The multiplier utilizing binary carry-save addition allows for an efficient pipelined implementation when latency and throughput are considered more important than area. Both designs comply with specifications for decimal multiplication given in the IEEE 754 Standard for Floating-Point Arithmetic (IEEE 754-2008). The multipliers extend previously published decimal fixed-point multipliers by adding several features, including exponent generation, sticky bit generation, shifting of the intermediate product, rounding, and exception detection and handling. Novel features of the multipliers include support for decimal floating-point numbers, on-the-fly generation of the sticky bit in the iterative design, early estimation of the shift amount, and efficient decimal rounding. Iterative and parallel decimal fixed-point and floating-point multipliers are compared in terms of their area, delay, latency, and throughput based on verified Verilog register-transfer-level models.

INDEX TERMS

Decimal multiplication, binary coded decimal, floating-point arithmetic, serial multiplication, parallel multiplication, pipelined multiplication.

CITATION

Mark A. Erle, Brian J. Hickmann, Michael J. Schulte, "Decimal Floating-Point Multiplication",

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