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Efficient Software-Based Encoding and Decoding of BCH Codes
July 2009 (vol. 58 no. 7)
pp. 878-889
Junho Cho, Seoul National University, Seoul
Wonyong Sung, Seoul National University, Seoul
Error correction software for Bose-Chaudhuri-Hochquenghem (BCH) codes is optimized for general purpose processors that do not equip hardware for Galois field arithmetic. The developed software applies parallelization with a table lookup method to reduce the number of iterations, and maximum parallelization under a cache size limitation is sought for a high throughput implementation. Since this method minimizes the number of lookup tables for encoding and decoding processes, a large parallel factor can be chosen for a given cache size. The naive word length of a general purpose CPU is used as a whole by employing the developed mask elimination method. The tradeoff of the algorithm complexity and the regularity is examined for several syndrome generation methods, which leads to a simple error detection scheme that reuses the encoder and a simplified syndrome generation method requiring only a small number of Galois field multiplications. The parallel factor for Chien search is increased much by transforming the error locator polynomial so that it contains symmetric exponents of positive and negative signs. The experimental results demonstrate that the developed software cannot only provide sufficient throughput for real-time error correction of NAND flash memory in embedded systems but also enhance the reliability of file systems in general purpose computers.

[1] H. Lee, “High-speed VLSI Architecture for Parallel Reed-Solomon Decoder,” IEEE Trans. VLSI System, vol. 11, no. 2, pp.288-294, Apr. 2003.
[2] L. Song, M.-L. Yu, M.S. Shaffer, “10- and 40-GB/s Forward Error Correction Devices for Optical Communications,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp.1565-1573, Nov. 2002.
[3] W. Liu, J. Rho, and W. Sung, “Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-level Cell NAND Flash Memories,” Proc. IEEE Workshop Signal Processing Systems (SiPS '06), pp.248-253, 2006.
[4] J. Rho, W. Liu, and W. Sung, “Lookup Table Based BCH Error Correction for Reliability Improvement of Multilevel Cell NAND Flash Memory,” Proc. Int'l Workshop Software Support Portable Storage (IWSSPS '06), Oct. 2006.
[5] T.V. Ramabadran, S.S. Gaitonde, “A Tutorial on CRC Computations,” IEEE Micro, vol. 8, no. 4, pp.62-75, Aug. 1988.
[6] D.V. Sarwate, “Computation of Cyclic Redundancy Checks via Table lookup,” Comm. ACM, vol. 31, pp.1008-1013, Aug. 1988.
[7] G. Albertengo, R. Sisto, “Parallel CRC Generation,” IEEE Micro, vol. 10, no. 5, pp.63-71, Oct. 1990.
[8] D.C. Feldmeier, “Fast Software Implementation of Error Detection Codes,” IEEE/ACM Trans. Networking, vol. 3, no. 6, pp.640-651, Dec. 1995.
[9] S.M. Sait and W. Hasan, “Hardware Design and VLSI Implementation of a Byte-Wise CRC Generator Chip,” IEEE Trans. Consumer Electronics, vol. 41, no. 1, pp.195-200, Feb. 1995.
[10] H.M. Ji and E. Killian, “Fast Parallel CRC Algorithm and Implementation on a Configurable Processor,” Proc. IEEE Int'l Conf. Comm. (ICC '02), vol. 3, pp.1813-1817, 2002.
[11] G. Campobello, G. Patane, and M. Russo, “Parallel CRC Realization,” IEEE Trans. Computers, vol. 52, no. 10, pp.1312-1319, Oct. 2003.
[12] C. Cheng and K.K. Parhi, “High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming,” IEEE Trans. Circuits and Systems II, vol. 53, no. 10, pp.1017-1021, Oct. 2006.
[13] J. Cho and W. Sung, “Software Implementation of Chien Search Process for Strong BCH Codes,” Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '08), May 2008.
[14] R.E. Blahut, Algebraic Codes for Data Transmission. Cambridge Univ. Press, 2003.
[15] S. Lin and D.J. Costello, Error Control Coding: Fundamentals and Applications, second ed. Prentice Hall, 2004.
[16] M. McLoone and J.V. McCanny, “Rijndael FPGA Implementation Utilizing lookup Tables,” Proc. IEEE Workshop Signal Processing Systems (SiPS '01), pp.349-360, Sept. 2001.
[17] X. Zhang and K.K. Parhi, “Implementation Approaches for the Advanced Encryption Standard Algorithm,” IEEE Circuits and Systems Magazine, vol. 2, no. 4, pp.24-46, fourth quarter 2002.
[18] H.M. Ji, “An Optimized Processor for Fast Reed-Solomon Encoding and Decoding,” Proc. IEEE Int'l Conf. Acoustics, Speech, and Signal Processing (ICASSP '02), pp. III-3097-III-3100, May 2002.
[19] A. Elbirt and C. Paar, “Efficient Implementation of Galois Field Fixed Field Constant Multiplication,” Proc. Int'l Conf. Information Technology (ITNG '06), pp.172-177, 2006.
[20] Intel 80200 Processor Based on Intel XScale Microarchitecture: Developer's Manual, Intel Corp., Mar. 2003.
[21] D.V. Sarwate and N.R. Shanbhag, “High-Speed Architectures for Reed-Solomon Decoders,” IEEE Trans. VLSI Systems, vol. 9, no. 5, pp.641-655, Oct. 2001.
[22] Performance Profiling Techniques on Intel XScale Microarchitecture Processors: Application Note, Intel Corp., Aug. 2002.
[23] A. Huffman, Flash Performance Enhancements Through ONFI. Open NAND Flash Interface, http://onfi.org/wp-content/uploads/2009/ 02memcon_performance_enhancements_through_onfi. pdf , Sept. 2006.

Index Terms:
BCH codes, CRC, software, implementation.
Citation:
Junho Cho, Wonyong Sung, "Efficient Software-Based Encoding and Decoding of BCH Codes," IEEE Transactions on Computers, vol. 58, no. 7, pp. 878-889, July 2009, doi:10.1109/TC.2009.27
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