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Process-Variation-Aware Adaptive Cache Architecture and Management
July 2009 (vol. 58 no. 7)
pp. 865-877
Madhu Mutyam, Indian Institute of Technology, Madras, Chennai
Feng Wang, Qualcomm Inc., San Diego
Ramakrishnan Krishnan, Penn State University, State College
Vijaykrishnan Narayanan, Pennsylvania State University, State College
Mahmut Kandemir, Pennsylvania State University, State College
Yuan Xie, Pennsylvania State University, State College
Mary Jane Irwin, Pennsylvania State University, State College
Fabricating circuits that employ ever-smaller transistors leads to dramatic variations in critical process parameters. This in turn results in large variations in execution/access latencies of different hardware components. This situation is even more severe for memory components due to minimum-sized transistors used in their design. Current design methodologies that are tuned for the worst case scenarios are becoming increasingly pessimistic from the performance angle, and thus, may not be a viable option at all for future designs. This paper makes two contributions targeting on-chip data caches. First, it presents an adaptive cache management policy based on nonuniform cache access. Second, it proposes a latency compensation approach that employs several circuit-level techniques to change the access latency of select cache lines based on the criticalities of the load instructions that access them. Our experiments reveal that both these techniques can recover significant amount of the lost performance due to worst case designs.

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Index Terms:
Process variation, cache, address prediction, superscalar processors.
Madhu Mutyam, Feng Wang, Ramakrishnan Krishnan, Vijaykrishnan Narayanan, Mahmut Kandemir, Yuan Xie, Mary Jane Irwin, "Process-Variation-Aware Adaptive Cache Architecture and Management," IEEE Transactions on Computers, vol. 58, no. 7, pp. 865-877, July 2009, doi:10.1109/TC.2009.30
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