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Fatih Kocan, Lun Li, Daniel G. Saab, "Exact Path Delay Fault Coverage Calculation of Partitioned Circuits," IEEE Transactions on Computers, vol. 58, no. 6, pp. 858864, June, 2009.  
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@article{ 10.1109/TC.2008.205, author = {Fatih Kocan and Lun Li and Daniel G. Saab}, title = {Exact Path Delay Fault Coverage Calculation of Partitioned Circuits}, journal ={IEEE Transactions on Computers}, volume = {58}, number = {6}, issn = {00189340}, year = {2009}, pages = {858864}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.205}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Exact Path Delay Fault Coverage Calculation of Partitioned Circuits IS  6 SN  00189340 SP858 EP864 EPD  858864 A1  Fatih Kocan, A1  Lun Li, A1  Daniel G. Saab, PY  2009 KW  Path delay fault KW  partitioned circuits KW  nonenumerative KW  exact coverage KW  ZBDD KW  graph theory. VL  58 JA  IEEE Transactions on Computers ER   
[1] G.L. Smith, “Model for Delay Faults Based upon Paths,” Proc. Int'l Test Conf. (ITC '85), pp. 342349, 1985.
[2] S. Padmanaban, M.K. Michael, and S. Tragoudas, “Exact Path Delay Fault Coverage with Fundamental ZBDD Operations,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 22, no. 3, pp. 305316, Mar. 2003.
[3] F. Kocan and M.H. Gunes, “On the ZBDDBased Nonenumerative Path Delay Fault Coverage Calculation,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 24, no. 7, pp. 11371143, July 2005.
[4] F. Kocan, M.H. Gunes, and A. Kurt, “OnLine Pruning of ZBDD for Path Delay Fault Coverage Calculation,” IEICE Trans. Information and Systems, vol. E88D, no. 7, pp. 13811388, 2005.
[5] D. Kagaris and S. Tragoudas, “On the Nonenumerative Path Delay Fault Simulation Problem,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 21, no. 9, pp. 10951101, Sept. 2002.
[6] M.A. Gharabeh, M.L. Bushnell, and V.D. Agrawal, “The PathStatus Graph with Application to Delay Fault Simulation,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 17, no. 4, pp. 324332, Apr. 1998.
[7] S. Minato, “ZeroSuppressed BDDs for Set Manipulation in Combinatorial Problems,” Proc. 30th Design Automation Conf. (DAC '93), pp. 272277, 1993.
[8] I. Pomeranz and S.M. Reddy, “An Efficient Nonenumerative Method to Estimate the Path Delay Fault Coverage in Combinational Circuits,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 13, no. 2, pp. 240250, Feb. 1998.
[9] F. Somenzi, “CUDD: CU Decision Diagram Package,” Dept. Electrical and Computer Eng., Univ. of Colorado, Boulder.
[10] A. Mishchenko, “Extra CUDD Package,” Dept. Electrical and Computer Eng., Portland State Univ., 2008.
[11] M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for Digital, Memory, and MixedSignal VLSI Circuits. Kluwer Academic Publishers, ISBN: 0792379918, 2005.
[12] S. Padmanaban and S. Tragoudas, “Efficient Identification of (Critical) Testable Path Delay Faults Using Decision Diagrams,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 24, no. 1, pp.7787, Jan. 2005.
[13] H.C. Wittmann and M. Henftling, “Efficient Path Identification for Delay Testing—Time and Space Optimization,” Proc. European Conf. Design Automation, European Test Conf., and European Event in ASIC Design (EDACETCEUROASIC '94), pp. 513517, 1994.
[14] K. Heragu, V.D. Agrawal, M.L. Bushnell, and J.H. Patel, “Improving a Nonenumerative Method to Estimate Path Delay Fault Coverage,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 16, no. 7, pp. 759762, July 1997.
[15] S.S. Skiena, The Algorithm Design Manual, first ed. Springer, ISBN10: 0387948600, July 1998.
[16] Fatih Kocan, http://engr.smu.edu/~kocangroup.html, 2008.