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Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
June 2009 (vol. 58 no. 6)
pp. 744-758
Sooyong Kang, Hanyang University, Seoul
Sungmin Park, Hanyang University, Seoul
Hoyoung Jung, Hanyang University, Seoul
Hyoki Shim, Hanyang University, Seoul
Jaehyuk Cha, Hanyang University, Seoul
While NAND flash memory is used in a variety of end-user devices, it has a few disadvantages, such as asymmetric speed of read and write operations, inability to in-place updates, among others. To overcome these problems, various flash-aware strategies have been suggested in terms of buffer cache, file system, FTL, and others. Also, the recent development of next-generation nonvolatile memory types such as MRAM, FeRAM, and PRAM provide higher commercial value to Non-Volatile RAM (NVRAM). At today's prices, however, they are not yet cost-effective. In this paper, we suggest the utilization of small-sized, next-generation NVRAM as a write buffer to improve the overall performance of NAND flash memory-based storage systems. We propose various block-based NVRAM write buffer management policies and evaluate the performance improvement of NAND flash memory-based storage systems under each policy. Also, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed buffer management policies outperform the traditional page-based LRU algorithm and the proposed optimistic FTL outperforms previous log block-based FTL algorithms, such as BAST and FAST.

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Index Terms:
Nonvolatile RAM, flash memory, write buffer, flash translation layer, solid-state disk, storage device.
Citation:
Sooyong Kang, Sungmin Park, Hoyoung Jung, Hyoki Shim, Jaehyuk Cha, "Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices," IEEE Transactions on Computers, vol. 58, no. 6, pp. 744-758, June 2009, doi:10.1109/TC.2008.224
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