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Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
June 2009 (vol. 58 no. 6)
pp. 744-758
ASCII Text
x 
 
Sooyong Kang, Sungmin Park, Hoyoung Jung, Hyoki Shim, Jaehyuk Cha, "Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices," IEEE Transactions on Computers, vol. 58, no. 6, pp. 744-758, June, 2009.
 
 
BibTex
x
 
@article{ 10.1109/TC.2008.224,
author = {Sooyong Kang and Sungmin Park and Hoyoung Jung and Hyoki Shim and Jaehyuk Cha},
title = {Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices},
journal ={IEEE Transactions on Computers},
volume = {58},
number = {6},
issn = {0018-9340},
year = {2009},
pages = {744-758},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.224},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
IS - 6
SN - 0018-9340
SP744
EP758
EPD - 744-758
A1 - Sooyong Kang,
A1 - Sungmin Park,
A1 - Hoyoung Jung,
A1 - Hyoki Shim,
A1 - Jaehyuk Cha,
PY - 2009
KW - Nonvolatile RAM
KW - flash memory
KW - write buffer
KW - flash translation layer
KW - solid-state disk
KW - storage device.
VL - 58
JA - IEEE Transactions on Computers
ER -
 
Sooyong Kang, Hanyang University, Seoul
Sungmin Park, Hanyang University, Seoul
Hoyoung Jung, Hanyang University, Seoul
Hyoki Shim, Hanyang University, Seoul
Jaehyuk Cha, Hanyang University, Seoul
While NAND flash memory is used in a variety of end-user devices, it has a few disadvantages, such as asymmetric speed of read and write operations, inability to in-place updates, among others. To overcome these problems, various flash-aware strategies have been suggested in terms of buffer cache, file system, FTL, and others. Also, the recent development of next-generation nonvolatile memory types such as MRAM, FeRAM, and PRAM provide higher commercial value to Non-Volatile RAM (NVRAM). At today's prices, however, they are not yet cost-effective. In this paper, we suggest the utilization of small-sized, next-generation NVRAM as a write buffer to improve the overall performance of NAND flash memory-based storage systems. We propose various block-based NVRAM write buffer management policies and evaluate the performance improvement of NAND flash memory-based storage systems under each policy. Also, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed buffer management policies outperform the traditional page-based LRU algorithm and the proposed optimistic FTL outperforms previous log block-based FTL algorithms, such as BAST and FAST.

[1] S.-Y. Park, D. Jung, J.-U. Kang, J.-S. Kim, and J. Lee, “CFLRU: A Replacement Algorithm for Flash Memory,” Proc. Int'l Conf. Compilers, Architecture, and Synthesis for Embedded Systems, Oct. 2006.
[2] H. Jo, J.-U. Kang, S.-Y. Park, J.-S. Kim, and J. Lee, “FAB: Flash-Aware Buffer Management Policy for Portable Media Players,” IEEE Trans. Consumer Electronics, vol. 52, no. 2, pp. 485-493, May 2006.
[3] M. Baker, S. Asami, E. Deprit, J. Ousterhout, M. Seltzer, “Non-Volatile Memory for Fast, Reliable File Systems,” Operating Systems Rev., vol. 26, pp.10-22, Oct. 1992.
[4] J.-F. Paris, T.R. Haining, and D.E. Long, “A Stack Model Based Replacement Policy for A Non-Volatile Cache,” Proc. IEEE Symp. Mass Storage Systems, pp.217-224, Mar. 2000.
[5] B. Gill and D.S. Modha, “WOW: Wise Ordering for Writes Combining Spatial and Temporal Locality in Non-Volatile Caches,” Proc. USENIX Conf. File and Storage Technologies (FAST), Dec. 2005.
[6] M. Wu and W. Zwaenepoel, “eNVy: A Non-Volatile, Main Memory Storage System,” Proc. Sixth Int'l Conf. Architectural Support for Programming Languages and Operating Systems, 1994.
[7] F. Douglis, F. Kaashoek, K. Li, R. Cceres, B. Marsh, and J.A. Tauber, “Storage Alternatives for Mobile Computers,” Proc. Operating Systems Design and Implementation, 1994.
[8] K. Kim and G.-H. Koh, “Future Memory Technology Including Emerging New Memories,” Proc. Int'l Conf. Microelectronics, May 2004.
[9] “Samsung Electronics 1gx8bit/2gx16bit NAND Flash Memory,” http://www.samsung.com/Products/Semiconductor/ NAND-Flash/SLCLargeBlock/16Gbit/K9WAG08U1M K9WA G08U1M.htm, 2009.
[10] http://www.techshout.com/hardware/2006/14 512mbit-pram-phase-change-ram-announced-by-samsung /, 2009.
[11] F.B. et al, “A Multi-Level-Cell Bipolar-Selected Phase-Change Memory,” Proc. Int'l Solid State Circuits Conf., Feb. 2008.
[12] Intel Corporation, “Understanding the Flash Translation Layer (FTL) Specification,” 1998.
[13] T. Shinohara, “Flash Memory Card with Block Memory Address Arrangement,” US Patent no. 5,905,993, 1999.
[14] M-Systems, “Flash-Memory Translation Layer for NAND Flash (NFTL).”
[15] L.-P. Chang and T.-W. Kuo, “An Adaptive Stripping Architecture for Flash Memory Storage Systems of Embedded Systems,” Proc. IEEE Eighth Real-Time and Embedded Technology and Applications Symp. (RTAS), Sept. 2002.
[16] J. Kim, J.M. Kim, S.H. Noh, S.L. Min, and Y. Cho, “A Space-Efficient Flash Translation Layer for Compact Flash Systems,” IEEE Trans. Consumer Electronics, vol. 48, no. 2, pp. 366-375, May 2002.
[17] S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song, “A Log Buffer Based Flash Translation Layer Using Fully Associative Sector Translation,” ACM Trans. Embedded Computing Systems, vol. 6, no. 3, 2007.
[18] E. Gal and, S. Toledo, “Algorithms and Data Structures for Flash Memories,” ACM Computing Surveys, vol. 37, no. 2 pp.138-163, June 2005.
[19] Aleph One Company “Yet Another Flash Filing System.”
[20] D. Woodhouse, “JFFS: The Journaling Flash File System.”
[21] J.-U. Kang, H. Jo, J.-S. Kim, and J. Lee, “A Superblock-Based Flash Translation Layer for NAND Flash Memory,” Proc. Sixth Ann. ACM Conf. Embedded Systems Software, Oct. 2006.
[22] H. Kim and S. Ahn, “BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage,” Proc. Sixth USENIX Conf. File and Storage Technologies, Feb. 2008.
[23] Embedded Systems and Wireless Networking Lab., http://news lab.csie.ntu.edu.tw/~flashindex.php?SelectedItem=Traces .

Index Terms:
Nonvolatile RAM, flash memory, write buffer, flash translation layer, solid-state disk, storage device.
Citation:
Sooyong Kang, Sungmin Park, Hoyoung Jung, Hyoki Shim, Jaehyuk Cha, "Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices," IEEE Transactions on Computers, vol. 58, no. 6, pp. 744-758, June 2009, doi:10.1109/TC.2008.224
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