|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| David Baneres, Jordi Cortadella, Mike Kishinevsky, "A Recursive Paradigm to Solve Boolean Relations," IEEE Transactions on Computers, vol. 58, no. 4, pp. 512-527, April, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.2008.165, author = {David Baneres and Jordi Cortadella and Mike Kishinevsky}, title = {A Recursive Paradigm to Solve Boolean Relations}, journal ={IEEE Transactions on Computers}, volume = {58}, number = {4}, issn = {0018-9340}, year = {2009}, pages = {512-527}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.165}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Recursive Paradigm to Solve Boolean Relations IS - 4 SN - 0018-9340 SP512 EP527 EPD - 512-527 A1 - David Baneres, A1 - Jordi Cortadella, A1 - Mike Kishinevsky, PY - 2009 KW - Boolean relations KW - logic synthesis KW - Boolean minimization KW - decomposition. VL - 58 JA - IEEE Transactions on Computers ER - | |||
[1] P. Agrawal, V.D. Agrawal, and N.N. Biswas, “Multiple Output Minimization,” Proc. 22nd ACM/IEEE Design Automation Conf. (DAC '85), pp. 674-680, 1985.
[2] D. Baneres, J. Cortadella, and M. Kishinevsky, “A Recursive Paradigm to Solve Boolean Relations,” Proc. 41st ACM/IEEE Design Automation Conf. (DAC '04), pp. 416-421, June 2004.
[3] T. Bartee, “Computer Design of Multiple-Output Logical Networks,” IRE Trans. Electronic Computers, vol. 10, pp. 21-30, 1961.
[4] L. Benini and G.D. Micheli, “A Survey of Boolean Matching Techniques for Library Binding,” ACM Trans. Design Automation of Electronic Systems, vol. 2, no. 3, pp. 193-226, July 1997.
[5] K.S. Brace, R.L. Rudell, and R.E. Bryant, “Efficient Implementation of a BDD Package,” Proc. 27th ACM/IEEE Design Automation Conf. (DAC '90), pp. 40-45, 1990.
[6] R. Brayton and F. Somenzi, “An Exact Minimizer for Boolean Relations,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '89), pp. 316-319, Nov. 1989.
[7] R. Brayton and F. Somenzi, “Minimization of Boolean Relations,” Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '89), pp. 738-743, 1989.
[8] R.K. Brayton, G.D. Hachtel, C.T. McMullen, and A. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984.
[9] F. Brown, Boolean Reasoning: The Logic of Boolean Equations. Kluwer Academic Publishers, 1990.
[10] M. Chrzanowska-Jeske, “Generalized Symmetric Variables,” Proc. Eighth IEEE Int'l Conf. Electronics, Circuits and Systems (ICECS '01), pp. 1147-1150, 2001.
[11] E.F. Codd, “Further Normalization of the Data Base Relational Model,” Courant Computer Science Symposia 6, “Data Base Systems”. Prentice Hall, May 1971.
[12] O. Coudert, “Two-Level Logic Minimization: An Overview,” Integration, the VLSI J., vol. 17, no. 2, pp. 97-140, 1994.
[13] O. Coudert, C. Berthet, and J. Madre, “Verification of Synchronous Sequential Machines Using Boolean Functional Vectors,” Proc. IFIP Int'l Workshop Applied Formal Methods for Correct VLSI Design, pp. 111-128, Nov. 1989.
[14] O. Coudert and J. Madre, “A Unified Framework for the Formal Verification of Circuits,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '90), pp. 126-129, Nov. 1990.
[15] O. Coudert and J.C. Madre, “New Ideas for Solving Covering Problems,” Proc. 32nd ACM/IEEE Design Automation Conf. (DAC'95), pp. 641-646, 1995.
[16] R. Cutler and S. Muroga, “Useless Prime Implicants of Incompletely Specified Multiple-Output Switching Functions,” Int'l J. Parallel Programming, vol. 9, no. 4, 1980.
[17] M. Damiani, J. Yang, and G.D. Micheli, “Optimization of Combinational Logic Circuits Based on Compatible Gates,” IEEETrans. Computer-Aided Design, vol. 14, no. 11, pp. 1316-1327, Nov. 1995.
[18] A. Ghosh, S. Devadas, and A. Newton, “Heuristic Minimization of Boolean Relations Using Testing Techniques,” Proc. IEEE Int'l Conf. Computer Design (ICCD '90), Sept. 1990.
[19] Y. Hong, P.A. Beerel, J.R. Burch, and K.L. McMillan, “Safe BDD Minimization Using Don't Cares,” Proc. 34th ACM/IEEE Design Automation Conf. (DAC '97), pp. 208-213, 1997.
[20] S. Jeong and F. Somenzi, “A New Algorithm for the Binate Covering Problem and Its Application to the Minimization of Boolean Relations,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '92), pp. 417-420, Nov. 1992.
[21] B. Lin and F. Somenzi, “Minimization of Symbolic Relations,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '90), pp.88-91, Nov. 1990.
[22] E. McCluskey, “Minimization of Boolean Functions,” Bell System Technical J., vol. 35, pp. 1417-1444, 1956.
[23] G.D. Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.
[24] S. Minato, “Fast Generation of Prime-Irredundant Covers from Binary Decision Diagrams,” IEICE Trans. Fundamentals of Electronics, Comm. and Computer Sciences, vol. E76-A, no. 6, pp.967-973, June 1993.
[25] R. Rudell, “Logic Synthesis for VLSI Design,” PhD dissertation, Univ. of California, Berkeley, Apr. 1989.
[26] R.L. Rudell and A. Sangiovanni-Vincentelli, “Multi-Valued Minimisation for PLA Optimisation,” IEEE Trans. Computer-Aided Design, pp. 727-750, 1987.
[27] T. Sasao, “An Application of Multiple-Valued Logic to a Design of Programmable Logic Arrays,” Proc. Eighth IEEE Int'l Symp. Multiple-Valued Logic (ISMVL '78), pp. 65-72, 1978.
[28] A. Schrijver, Efficient Parallel Algorithms. John Wiley & Sons, 1998.
[29] E. Sentovich and D. Brand, “Flexibility in Logic,” Logic Synthesis and Verification, S. Hassoun and T. Sasao, eds., chapter 3, pp. 65-88, Kluwer Academic Publishers, 2002.
[30] E. Sentovich, V. Singhal, and R. Brayton, “Multiple Boolean Relations,” Proc. Int'l Workshop Logic Synthesis (IWLS '93), May 1993.
[31] E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, and A. Sangiovanni-Vincentelli, “SIS: A System for Sequential Circuit Synthesis,” technical report, Univ. of California, Berkeley, May 1992.
[32] H.J. Touati, Performance-Oriented Technology Mapping, Memorandum number ucb/erl m90/109, Electronics Research Laboratory, College of Eng., Univ. of California, Berkeley, Nov. 1990.
[33] Y. Watanabe and R. Brayton, “Heuristic Minimization of Multiple-Valued Relations,” IEEE Trans. Computer-Aided Design, vol. 12, no. 10, pp. 1458-1472, Oct. 1993.
[34] J.S. Zhang, M. Chrzanowska-Jeske, A. Mishchenko, and J.R. Burch, “Generalized Symmetries in Boolean Functions: Fast Computation and Application to Boolean Matching,” Proc. Int'l Workshop Logic Synthesis (IWLS '04), pp. 424-430, 2004.
[35] J.S. Zhang, A. Mishchenko, R. Brayton, and M. Chrzanowska-Jeske, “Symmetry Detection for Large Boolean Functions Using Circuit Representation, Simulation, and Satisfiability,” Proc. 43rd ACM/IEEE Design Automation Conf. (DAC '06), pp. 510-515, 2006.

