Issue No.04 - April (2009 vol.58)
Oliverio J. Santana , Universidad de Las Palmas de Gran Canaria, Las Palmas de Gran Canaria
Alex Ramirez , Universitat Politècnica de Catalunya, Barcelona
Mateo Valero , Universitat Politècnica de Catalunya, Barcelona
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2008.170
Fast instruction decoding is a true challenge for the design of CISC microprocessors implementing variable-length instructions. A well-known solution to overcome this problem is caching decoded instructions in a hardware buffer. Fetching already decoded instructions avoids the need for decoding them again, improving processor performance. However, introducing such special--purpose storage in the processor design involves an important increase in the fetch architecture complexity. In this paper, we propose a novel decoding architecture that reduces the fetch engine implementation cost. Instead of using a special-purpose hardware buffer, our proposal stores frequently decoded instructions in the memory hierarchy. The address where the decoded instructions are stored is kept in the branch prediction mechanism, enabling it to guide our decoding architecture. This makes it possible for the processor front end to fetch already decoded instructions from the memory instead of the original nondecoded instructions. Our results show that using our decoding architecture, a state-of-the-art superscalar processor achieves competitive performance improvements, while requiring less chip area and energy consumption in the fetch architecture than a hardware code caching mechanism.
Superscalar processor design, CISC instruction decoding, variable-length ISA, branch predictor, code caching.
Oliverio J. Santana, Alex Ramirez, Mateo Valero, "DIA: A Complexity-Effective Decoding Architecture", IEEE Transactions on Computers, vol.58, no. 4, pp. 448-462, April 2009, doi:10.1109/TC.2008.170