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Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling
March 2009 (vol. 58 no. 3)
pp. 409-423
ASCII Text
x 
 
Sandeep Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty, "Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling," IEEE Transactions on Computers, vol. 58, no. 3, pp. 409-423, March, 2009.
 
 
BibTex
x
 
@article{ 10.1109/TC.2008.169,
author = {Sandeep Goel and Erik Jan Marinissen and Anuja Sehgal and Krishnendu Chakrabarty},
title = {Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling},
journal ={IEEE Transactions on Computers},
volume = {58},
number = {3},
issn = {0018-9340},
year = {2009},
pages = {409-423},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.169},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling
IS - 3
SN - 0018-9340
SP409
EP423
EPD - 409-423
A1 - Sandeep Goel,
A1 - Erik Jan Marinissen,
A1 - Anuja Sehgal,
A1 - Krishnendu Chakrabarty,
PY - 2009
KW - Hardware
KW - Control Structure Reliability
KW - Testing
KW - and Fault-Tolerance
KW - Reliability
KW - Testing
KW - and Fault-Tolerance
VL - 58
JA - IEEE Transactions on Computers
ER -
 
Sandeep Goel, Magma Design Automation, San Jose
Erik Jan Marinissen, NXP Semiconductors, Eindhoven
Anuja Sehgal, AMD, Sunnyvale
Krishnendu Chakrabarty, Duke University, Durham
Many system-on-chip (SOC) integrated circuits today contain hierarchical (parent) cores that have multiple levels of design hierarchy involving "child cores". Hierarchy imposes a number of constraints on the manner in which tests must be applied to parent cores and their child cores. However, most prior work on wrapper design, test access mechanism (TAM) optimization, and test scheduling are hierarchy-oblivious, i.e., these techniques treat all cores in an SOC at the same level of hierarchy. We first show that wrappers, TAMs and test schedules designed for non-hierarchical SOCs are not valid for SOCs with hierarchical cores. We next present two approaches for the efficient testing of SOC with hierarchical cores. In the first approach, an existing wrapper design is modified such that that all constraints imposed by the hierarchy are satisfied and full flexibility is provided for TAM optimization and test scheduling. The second approach is based on a hierarchy-aware wrapper architecture for parent cores that operates in two disjoint modes for the testing of parent and child cores. We show how an existing test-architecture design algorithm can be adapted for use with these two methods. Results for the ITC'02 SOC Test Benchmarks show that the first approach offers lower test application times while the second approach requires less area overhead.

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Index Terms:
Hardware, Control Structure Reliability, Testing, and Fault-Tolerance, Reliability, Testing, and Fault-Tolerance
Citation:
Sandeep Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty, "Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling," IEEE Transactions on Computers, vol. 58, no. 3, pp. 409-423, March 2009, doi:10.1109/TC.2008.169
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