This Article 
 Bibliographic References 
 Add to: 
Hardware Designs for Decimal Floating-Point Addition and Related Operations
March 2009 (vol. 58 no. 3)
pp. 322-335
Liang-Kai Wang, AMD, Austin
Michael J. Schulte, University of Wisconsin-Madison, Madison
John D. Thompson, Cray Inc., Chippewa Falls
Nandini Jairam, Intel Corporation, Folsom
Decimal arithmetic is often used in commercial, financial, and Internet-based applications. Due to the growing importance of decimal floating-point (DFP) arithmetic, the IEEE 754 Draft Standard for Floating-Point Arithmetic (IEEE P754) includes specifications for DFP arithmetic. This paper gives an overview of DFP arithmetic in IEEE P754 and discusses previous research on decimal fixed-point and floating-point addition. It also presents novel designs for a DFP adder and a DFP multifunction unit (DFP MFU) that comply with IEEE P754. To reduce their delay, the DFP adder and MFU both use decimal injection-based rounding, a new form of decimal operand alignment, and a fast flag-based method for rounding and overflow detection. Synthesis results indicate that the proposed DFP adder is roughly 21% faster and 1.6% smaller than a previous DFP adder design, when implemented in the same technology. Compared to the DFP adder, the DFP MFU provides six additional operations, yet only has 2.8% more delay and 9.7% more area. A pipelined version of the DFP MFU has a latency of six cycles, a throughput of one result per cycle, an estimated critical path delay of 12.9 fanout-offour (FO4) inverter delays, and an estimated area of 0.2953mm2.

[1] IEEE, IEEE 754-2008 Standard for Floating-Point Arithmetic, 2008.
[2] L. Eisen, J.W. Ward III, H.-W. Tast, N. Mading, J. Leenstra, S.M. Mueller, C. Jacobi, J. Preiss, E.M. Schwarz, and S.R. Carlough, “IBM POWER6 Accelerators: VMX and DFU,” IBM J. Research and Development, vol. 51, no. 6, pp. 663-684, 2007.
[3] A.Y. Duale, M.H. Decker, H.-G. Zipperer, M. Aharoni, and T.J. Bohizic, “Decimal Floating-Point in z9: An Implementation and Testing Perspective,” IBM J. Research and Development, vol. 51, nos. 1/2, pp. 217-228, 2007.
[4] C.F. Webb, “IBM z10: The Next-Generation Mainframe Microprocessor,” IEEE Micro, vol. 28, no. 2, pp. 19-29, Mar./Apr. 2008.
[5] P.M. Kogge and H.S. Stone, “A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations,” IEEE Trans. Computers, vol. C-22, no. 8, pp. 786-793, Aug. 1973.
[6] G. Even and P.M. Seidel, “A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication,” IEEE Trans. Computers, vol. 49, no. 7, pp. 638-650, July 2000.
[7] N. Burgess, “Prenormalization Rounding in IEEE Floating-Point Operations Using a Flagged Prefix Adder,” IEEE Trans. VLSI Systems, vol. 13, no. 2, pp. 266-277, Feb. 2005.
[8] Sun Microsystem, BigDecimal Class, Java 2 Platform Standard Edition 5.0, API Specification,, 2004.
[9] J. Thompson, M.J. Schulte, and N. Karra, “A 64-Bit Decimal Floating-Point Adder,” Proc. IEEE CS Ann. Symp. VLSI (ISVLSI '04), pp. 297-298, Feb. 2004.
[10] L.-K. Wang and M.J. Schulte, “Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding,” Proc. 18th IEEE Symp. Computer Arithmetic (ARITH '07), pp. 56-68, June 2007.
[11] IEEE Inc., IEEE 754-1985 Standard for Binary Floating-Point Arithmetic, 1985.
[12] M.F. Cowlishaw, Decimal Arithmetic FAQ: Part 1—General Questions, , 2003.
[13] R.K. Richards, Arithmetic Operations in Digital Computers. Van Nostrand, 1955.
[14] U. Grupe, Decimal Adder, US Patent 3,935,438, Jan. 1976.
[15] M.J. Adiletta and V.C. Lamere, BCD Adder Circuit, US Patent 4,805,131, Feb. 1989.
[16] H. Fischer and W. Rohsaint, Circuit Arrangement for Adding or Subtracting Operands in BCD-Code or Binary-Code, US Patent 5,146,423, Sept. 1992.
[17] M.S. Schmookler and A.W. Weinberger, “High Speed Decimal Addition,” IEEE Trans. Computers, vol. 20, pp. 862-867, Aug. 1971.
[18] L.-K. Wang, “Processor Support for Decimal Floating-Point Arithmetic,” PhD dissertation, Dept. Electrical and Computer Eng., University of Wisconsin-Madison, 2007.
[19] P.M. Seidel and G. Even, “Delay-Optimized Implementation of IEEE Floating-Point Addition,” IEEE Trans. Computers, vol. 53, no. 2, pp. 97-113, Feb. 2004.
[20] A. Beaumont-Smith and C.-C. Lim, “Parallel Prefix Adder Design,” Proc. 15th IEEE Symp. Computer Arithmetic (ARITH '01), pp. 218-225, 2001.
[21] IBM Corporation, The decNumber Library, http://www2.hursley. , version 3.56, Apr. 2008.
[22] Sy nopsys, Galaxy Design Platform, http:/, 2008.
[23] M. Cornea, C. Anderson, J. Harrison, P.T.P. Tang, E. Schneider, and C. Tsen, “A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format,” Proc. 18th IEEE Symp. Computer Arithmetic (ARITH '07), pp. 29-37, 2007.
[24] L.-K. Wang, C. Tsen, M.J. Schulte, and D. Jhalani, “Benchmarks and Performance Analysis for Decimal Floating-Point Applications,” Proc. 25th IEEE Int'l Conf. Computer Design (ICCD '07), pp.164-170, Oct. 2007.

Index Terms:
Arithmetic and logic units, Computer arithmetic, Algorithms, High-Speed Arithmetic, Arithmetic and Logic Structures, Hardware
Liang-Kai Wang, Michael J. Schulte, John D. Thompson, Nandini Jairam, "Hardware Designs for Decimal Floating-Point Addition and Related Operations," IEEE Transactions on Computers, vol. 58, no. 3, pp. 322-335, March 2009, doi:10.1109/TC.2008.147
Usage of this product signifies your acceptance of the Terms of Use.