
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Dimitri Tan, Carl E. Lemonds, Michael J. Schulte, "LowPower MultiplePrecision Iterative FloatingPoint Multiplier with SIMD Support," IEEE Transactions on Computers, vol. 58, no. 2, pp. 175187, February, 2009.  
BibTex  x  
@article{ 10.1109/TC.2008.203, author = {Dimitri Tan and Carl E. Lemonds and Michael J. Schulte}, title = {LowPower MultiplePrecision Iterative FloatingPoint Multiplier with SIMD Support}, journal ={IEEE Transactions on Computers}, volume = {58}, number = {2}, issn = {00189340}, year = {2009}, pages = {175187}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2008.203}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  LowPower MultiplePrecision Iterative FloatingPoint Multiplier with SIMD Support IS  2 SN  00189340 SP175 EP187 EPD  175187 A1  Dimitri Tan, A1  Carl E. Lemonds, A1  Michael J. Schulte, PY  2009 KW  Computer arithmetic KW  rectangular multiplier KW  floatingpoint arithmetic KW  lowpower KW  multiplying circuits KW  multimedia KW  verylargescale integration. VL  58 JA  IEEE Transactions on Computers ER   
[1] P. Ranganathan, S. Adve, and N. Jouppi, “Performance of Image and Video Processing with GeneralPurpose Processors and Media ISA Extensions,” Proc. 26th Ann. Int'l Symp. Computer Architecture (ISCA '99), vol. 27, pp. 124135, May 1999.
[2] S.K. Raman, V. Pentkovski, and J. Keshava, “Implementing Streaming SIMD Extensions on the Pentium III Processor,” IEEE Micro, vol. 20, pp. 4757, July 2000.
[3] M.L. Li, R. Sasanka, S. Adve, Y.K. Chen, and E. Debes, “The ALPBench Benchmark Suite for Complex Multimedia Applications,” Proc. IEEE Int'l Symp. Workload Characterization (IISWC '05), pp. 3445, Oct. 2005.
[4] H. Nguyen and L.K. John, “Exploiting SIMD Parallelism in DSP and Multimedia Algorithms Using the AltiVec Technology,” Proc. 13th Int'l Conf. Supercomputing (ICS '99), pp. 1120, June 1999.
[5] “Advanced Micro Devices,” AMD64 Architecture Programmer's Manual Volume 4: 128Bit Media Instructions, rev. 3.07 ed., Dec. 2005.
[6] “Advanced Micro Devices,” AMD64 Architecture Programmer's Manual Volume 5: 64Bit Media and x87 FloatingPoint Instructions, rev. 3.06 ed., Dec. 2005.
[7] J. Hennessy and D. Patterson, Computer Architecture: A QuantitativeApproach, ch. 2, third ed. Morgan Kaufmann, p.119, May 2002.
[8] S. Oberman, “FloatingPoint Division and Square Root Algorithms and Implementation in the AMDK7™ Microprocessor,” Proc. 14th IEEE Symp. Computer Arithmetic (ARITH '99), pp.106115, Apr. 1999.
[9] C. Keltcher, K. McGrath, A. Ahmed, and P. Conway, “The AMDOpteron Processor for Multiprocessor Servers,” IEEE Micro, vol. 23, pp. 6676, Mar. 2003.
[10] W. Briggs and D. Matula, “A 17 $\times$ 69 Bit Multiply and Add Unit with Redundant Binary Feedback and Single Cycle Latency,” Proc. 11th IEEE Symp. Computer Arithmetic (ARITH'93), pp. 163170, July 1993.
[11] M. Schulte, C. Lemonds, and D. Tan, “FloatingPoint Division Algorithms for an x86 Microprocessor with a Rectangular Multiplier,” Proc. IEEE Int'l Conf. Computer Design (ICCD '07), pp. 304310, Oct. 2007.
[12] ANSI and IEEE, IEEE754 Standard for Binary FloatingPoint Arithmetic, 1985.
[13] G. Hinton, M. Upton, D. Sager, D. Boggs, D. Carmean, P. Roussel, T. Chappell, T. Fletcher, M. Milshtein, M. Sprague, S. Samaan, and R. Murray, “A 0.18um CMOS IA32 Processor with a 4GHz Integer Execution Unit,” IEEE J. SolidState Circuits, vol. 36, pp.16171627, Nov. 2001.
[14] G. Even, S.M. Mueller, and P.M. Seidel, “A Dual Mode IEEE Multiplier,” Proc. Second Ann. IEEE Int'l Conf. Innovative Systems in Silicon (ISIS '97), pp. 282289, Oct. 1997.
[15] S. Vassiliadis, E. Schwarz, and B. Sung, “HardWired Multipliers with Encoded Partial Products,” IEEE Trans. Computers, vol. 40, pp. 11811197, Nov. 1991.
[16] A. Weinberger, “4:2 CarrySave Adder Module,” IBM Technical Disclosure Bull., vol. 23, pp. 38113814, Jan. 1981.
[17] S. Anderson, J. Earle, R. Goldschmidt, and D. Powers, “The IBM System/360 Model 91: FloatingPoint Execution Unit,” IBM J. Research and Development, vol. 11, pp. 3453, Jan. 1967.
[18] R.M. Jessani and M. Putrino, “Comparison of Single and DualPass MultiplyAdd Fused FloatingPoint Units,” IEEE Trans. Computers, vol. 47, pp. 927937, Sept. 1998.
[19] M.R. Santoro, G. Bewick, and M. Horowitz, “Rounding Algorithms for IEEE Multipliers,” Proc. Ninth IEEE Symp. Computer Arithmetic (ARITH '89), pp. 176183, Sept. 1989.
[20] G. Even and P.M. Seidel, “A Comparison of Three Rounding Algorithms for IEEE FloatingPoint Multiplication,” IEEE Trans. Computers, vol. 49, pp. 638650, July 2000.
[21] N.T. Quach, N. Takagi, and M. Flynn, “Systematic IEEE Rounding Method for HighSpeed FloatingPoint Multipliers,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, pp. 511521, May 2004.
[22] A. Enriques and K. Jones, “Design of a MultiMode Pipelined Multiplier for FloatingPoint Applications,” Proc. IEEE Nat'l Aerospace and Electronics Conf. (NAECON '91), vol. 1, pp. 7781, May 1991.
[23] A. Akkas and M. Schulte, “A Quadruple Precision and Dual Double Precision FloatingPoint Multiplier,” Proc. Euromicro Symp. Digital System Design (DSD '03), pp. 7681, Sept. 2003.
[24] D. Tan, A. Danysh, and M. Liebelt, “MultiplePrecision FixedPoint Vector MultiplyAccumulator Using Shared Segmentation,” Proc. 16th IEEE Symp. Computer Arithmetic (ARITH '03), pp. 1219, June 2003.
[25] S. Krithivasan and M.J. Schulte, “Multiplier Architectures for Media Processing,” Proc. IEEE 37th Asilomar Conf. Signals, Systems, and Computers (ACSSC '03), vol. 2, pp. 21932197, Nov. 2003.
[26] L. Huang, L. Shen, K. Dai, and Z. Wang, “A New Architecture forMultiplePrecision FloatingPoint MultiplyAdd Fused Unit Design,” Proc. 18th IEEE Symp. Computer Arithmetic (ARITH '07), pp. 6976, June 2007.